Product Information

GS8182Q18BGD-200I

GS8182Q18BGD-200I electronic component of GSI Technology

Datasheet
SRAM 1.8 or 1.5V 1M x 18 18M

Manufacturer: GSI Technology
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

144: USD 19.7346 ea
Line Total: USD 2841.7824

0 - Global Stock
MOQ: 144  Multiples: 144
Pack Size: 144
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 144
Multiples : 144

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GS8182Q18BGD-200I
GSI Technology

144 : USD 22.8045

     
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RoHS - XON
Icon ROHS
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GS8182Q08/09/18/36BD-333/300/250/200/167/133 165-Bump BGA 333 MHz133 MHz TM 18Mb SigmaQuad-II Commercial Temp 1.8 V V DD Industrial Temp 1.8 V and 1.5 V I/O Burst of 2 SRAM Features Clocking and Addressing Schemes Simultaneous Read and Write SigmaQuad Interface The GS8182Q08/09/18/36BD SigmaQuad-II SRAMs are JEDEC-standard pinout and package synchronous devices. They employ two input register clock Dual Double Data Rate interface inputs, K and K. K and K are independent single-ended clock Byte Write controls sampled at data-in time inputs, not differential inputs to a single differential clock input Burst of 2 Read and Write buffer. The device also allows the user to manipulate the 1.8 V +100/100 mV core power supply output register clock inputs quasi independently with the C and 1.5 V or 1.8 V HSTL Interface C clock inputs. C and C are also independent single-ended Pipelined read operation clock inputs, not differential inputs. If the C clocks are tied Fully coherent read and write pipelines high, the K clocks are routed internally to fire the output ZQ pin for programmable output drive strength registers instead. IEEE 1149.1 JTAG-compliant Boundary Scan Pin-compatible with present 9Mb and future 36Mb and Each internal read and write operation in a SigmaQuad-II B2 144Mb devices RAM is two times wider than the device I/O bus. An input data 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package bus de-multiplexer is used to accumulate incoming data before RoHS-compliant 165-bump BGA package available it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate SigmaQuad Family Overview output drivers as needed. Therefore the address field of a The GS8182Q08/09/18/36BD are built in compliance with SigmaQuad-II B2 RAM is always one address pin less than the the SigmaQuad-II SRAM pinout standard for Separate I/O advertised index depth (e.g., the 2M x 8 has a 1M addressable synchronous SRAMs. They are 18,874,368-bit (18Mb) index). SRAMs. The GS8182Q08/09/18/36BD SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Parameter Synopsis -333 -300 -250 -200 -167 -133 tKHKH 3.0ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 7.5 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.5 ns 0.5 ns Rev: 1.03d 11/2011 1/36 2007, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8182Q08/09/18/36BD-333/300/250/200/167/133 512K x 36 SigmaQuad-II SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA NC/SA NC/SA A CQ W BW2 K BW1 R CQ (288Mb) (72Mb) (36Mb) (144Mb) B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 V SA SA SA V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V SA SA SA V Q10 D9 D1 SS SS P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI 2 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Note: BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35 Rev: 1.03d 11/2011 2/36 2007, GSI Technology Specifications cited are subject to change without notice. For latest documentation see

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory

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