A29040C Series 512K X 8 Bit CMOS 5.0 Volt-only, Preliminary Uniform Sector Flash Memory Document Title 512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory Revision History Rev. No. History Issue Date Remark 0.0 Initial issue May 27, 2013 Preliminary PRELIMINARY (May, 2013, Version 0.0) AMIC Technology, Corp. A29040C Series 512K X 8 Bit CMOS 5.0 Volt-only, Preliminary Uniform Sector Flash Memory Features - Embedded Program algorithm automatically writes and 5.0V 10% for read and write operations verifies bytes at specified addresses Access times: - 55/70 (max.) Minimum 100,000 program/erase cycles per sector 10-year data retention Current: - Reliable operation for the life of the system - 20 mA typical active read current - 30 mA typical program/erase current Compatible with JEDEC-standards - Pinout and software compatible with single-power- - 1 A typical CMOS standby supply Flash memory standard Flexible sector architecture - Superior inadvertent write protection - 8 uniform sectors of 64 Kbyte each - Any combination of sectors can be erased Data Polling and toggle bits - Supports full chip erase - Provides a software method of detecting completion of - Sector protection: program or erase operations A hardware method of protecting sectors to prevent Erase Suspend/Erase Resume any inadvertent program or erase operations within that - Suspends a sector erase operation to read data from, sector or program data to, a non-erasing sector, then Extended operating temperature range: -40C~+85C resumes the erase operation for U series Package options Embedded Erase Algorithms - 32-pin P-DIP, PLCC, or TSOP (Forward type) - Embedded Erase algorithm will automatically erase the - All Pb-free (Lead-free) products are RoHS compliant entire chip or any combination of designated sectors and verify the erased sectors General Description Reading data out of the device is similar to reading from The A29040C is a 5.0 volt-only Flash memory organized as other Flash or EPROM devices. 524,288 bytes of 8 bits each. The 512 Kbytes of data are further divided into eight sectors of 64 Kbytes each for flexible Device programming occurs by writing the proper program sector erase capability. The 8 bits of data appear on I/O0 - command sequence. This initiates the Embedded Program I/O7 while the addresses are input on A0 to A18. The algorithm - an internal algorithm that automatically times the A29040C is offered in 32-pin PLCC, TSOP, and PDIP program pulse widths and verifies proper program margin. packages. This device is designed to be programmed in- Device erasure occurs by executing the proper erase system with the standard system 5.0volt VCC supply. command sequence. This initiates the Embedded Erase Additional 12.0 volt VPP is not required for in-system write or algorithm - an internal algorithm that automatically erase operations. However, the A29040C can also be preprograms the array (if it is not already programmed) programmed in standard EPROM programmers. before executing the erase operation. During erase, the The A29040C has a second toggle bit, I/O2, to indicate device automatically times the erase pulse widths and whether the addressed sector is being selected for erase, and verifies proper erase margin. also offers the ability to program in the Erase Suspend mode. The host system can detect whether a program or erase The standard A29040C offers access times of 55 and 70 ns, operation is complete by reading the I/O7 ( Polling) and Data allowing high-speed microprocessors to operate without wait I/O6 (toggle) status bits. After a program or erase cycle has states. To eliminate bus contention the device has separate been completed, the device is ready to read array data or chip enable ( ), write enable ( ) and output enable CE WE accept another command. The sector erase architecture allows memory sectors to be ( ) controls. OE erased and reprogrammed without affecting the data The device requires only a single 5.0 volt power supply for contents of other sectors. The A29040C is fully erased when both read and write functions. Internally generated and shipped from the factory. regulated voltages are provided for the program and erase The hardware sector protection feature disables operations operations. for both program and erase in any combination of the sectors The A29040C is entirely software command set compatible of memory. This can be achieved via programming with the JEDEC single-power-supply Flash standard. equipment. Commands are written to the command register using The Erase Suspend feature enables the user to put erase on standard microprocessor write timings. Register contents hold for any period of time to read data from, or program serve as input to an internal state-machine that controls the data to, any other sector that is not selected for erasure. erase and programming circuitry. True background erase can thus be achieved. Write cycles also internally latch addresses and data Power consumption is greatly reduced when the device is needed for the programming and erase operations. placed in the standby mode. PRELIMINARY (May, 2013, Version 0.0) 1 AMIC Technology, Corp.