Variable Resolution, Monolithic a Resolver-to-Digital Converter AD2S80A FEATURES FUNCTIONAL BLOCK DIAGRAM Monolithic (BiMOS ll) Tracking R/D Converter 40-Lead DIP Package 44-Terminal LCC Package 10-,12-,14-, and 16-Bit Resolution Set by User Ratiometric Conversion Low Power Consumption: 300 mW Typ AD2S80A SIN I/P A1 A3 Dynamic Performance Set by User INTEGRATOR SIG GND SEGMENT R-2R High Max Tracking Rate 1040 RPS (10 Bits) O/P SWITCHING DAC PHASE Velocity Output COS I/P A2 SENSITIVE ANALOG DETECTOR Industrial Temperature Range Versions GND Military Temperature Range Versions RIPPLE VCO DATA CLK 16-BIT UP/DOWN COUNTER TRANSFER VCO I/P ESD Class 2 Protection (2,000 V Min) DATA LOGIC LOAD /883 B Parts Available +12V OUTPUT DATA LATCH 12V APPLICATIONS DC Brushless and AC Motor Control Process Control 16 DATA BITS Numerical Control of Machine Tools Robotics Axis Control PRODUCT HIGHLIGHTS Military Servo Control Monolithic. A one chip solution reduces the package size required and increases the reliability. GENERAL DESCRIPTION Resolution Set by User. Two control pins are used to select The AD2S80A is a monolithic 10-, 12-, 14-, or 16-bit tracking the resolution of the AD2S80A to be 10, 12, 14, or 16 bits allowing resolver-to-digital converter contained in a 40-lead DIP or 44- the user to use the AD2S80A with the optimum resolution for terminal LCC ceramic package. It is manufactured on a BiMOS each application. II process that combines the advantages of CMOS logic and bipolar high accuracy linear circuits on the same chip. Ratiometric Tracking Conversion. Conversion technique provides continuous output position data without conversion The converter allows users to select their own resolution and dynamic delay and is insensitive to absolute signal levels. It also provides performance with external components. This allows the users great good noise immunity and tolerance to harmonic distortion on flexibility in defining the converter that best suits their system the reference and input signals. requirements. The converter allows users to select the resolution to be 10, 12, 14, or 16 bits and to track resolver signals rotating Dynamic Performance Set by the User. By selecting exter- at up to 1040 revs per second (62,400 rpm) when set to 10-bit nal resistor and capacitor values the user can determine bandwidth, resolution. maximum tracking rate and velocity scaling of the converter to match the system requirements. The external components The AD2S80A converts resolver format input signals into a required are all low cost preferred value resistors and capacitors, parallel natural binary digital word using a ratiometric tracking and the component values are easy to select using the simple conversion method. This ensures high-noise immunity and toler- instructions given. ance of lead length when the converter is remote from the resolver. Velocity Output. An analog signal proportional to velocity is The 10-, 12-, 14- or 16-bit output word is in a three-state digital available and is linear to typically one percent. This can be used logic available in 2 bytes on the 16 output data lines. BYTE in place of a velocity transducer in many applications to provide SELECT, ENABLE and INHIBIT pins ensure easy data trans- loop stabilization in servo controls and velocity feedback data. fer to 8- and 16-bit data buses, and outputs are provided to allow for cycle or pitch counting in external counters. Low Power Consumption. Typically only 300 mW. An analog signal proportional to velocity is also available and Military Product. The AD2S80A is available processed in can be used to replace a tachogenerator. accordance with MIL-STD-883B, Class B. The AD2S80A operates over 50 Hz to 20,000 Hz reference MODELS AVAILABLE frequency. Information on the models available is given in the section Ordering Information. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 www.analog.com otherwise under any patent or patent rights of Analog Devices. Analog Devices, Inc., 19862015 SC1 SC2 ENABLE AC ERROR O/P BYTE SELECT DEMOD I/P 5V REF I/P DIG GND DEMOD O/P BUSY DIR INTEGRATOR INHIBIT I/P(typical at 25 C unless otherwise noted) AD2S80ASPECIFICATIONS Parameter Conditions Min Typ Max Unit SIGNAL INPUTS Frequency 50 20,000 Hz Voltage Level 1.8 2.0 2.2 V rms Input Bias Current 60 150 nA Input Impedance 1.0 M Maximum Voltage 8V pk REFERENCE INPUT Frequency 50 20,000 Hz Voltage Level 1.0 8.0 V pk Input Bias Current 60 150 nA Input Impedance 1.0 M CONTROL DYNAMICS Repeatability 1 LSB Allowable Phase Shift (Signals to Reference) 10 +10 Degrees Tracking Rate 10 Bits 1040 rps 12 Bits 260 rps 14 Bits 65 rps 16 Bits 16.25 rps 1 Bandwidth User Selectable ACCURACY Angular Accuracy A, J, S 8 +1 LSB arc min B, K, T 4 +1 LSB arc min L, U 2 +1 LSB arc min Monotonicity Guaranteed Monotonic Missing Codes (16-Bit Resolution) A, B, J, K, S, T 4 Codes L, U 1 Code VELOCITY SIGNAL Linearity Over Full Range 1 3 % FSD Reversion Error 1 2 % FSD 2 DC Zero Offset 6 mV DC Zero Offset Tempco 22 V/C Gain Scaling Accuracy 10 % FSD Output Voltage 1 mA Load 8 9 10.5 V Dynamic Ripple Mean Value 1.5 % rms O/P Output Load 1.0 k INPUT/OUTPUT PROTECTION Analog Inputs Overvoltage Protection 8V Analog Outputs Short Circuit O/P Protection 5.6 8 10.4 mA DIGITAL POSITION Resolution 10, 12, 14, and 16 Output Format Bidirectional Natural Binary Load 3 LSTTL 3 INHIBIT Sense Logic LO to Inhibit Time to Stable Data 600 ns 3 ENABLE Logic LO Enables Position Output. Logic HI Outputs in ENABLE Time High Impedance State 35 110 ns 3 BYTE SELECT Sense MS Byte DB1DB8, LS Byte DB9DB16 LOGIC LO LS Byte DB1DB8, LS Byte DB9DB16 Time to Data Available 60 140 ns SHORT CYCLE INPUTS Internally Pulled High (100 k ) to +V S SC1 SC2 0 0 10 Bit 0 1 12 Bit 1 0 14 Bit 1 1 16 Bit 2 REV. D