12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9613 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD SNR = 69.6 dBFS at 185 MHz f and 250 MSPS IN SFDR = 86 dBc at 185 MHz f and 250 MSPS IN VIN+A PIPELINE 149.9 dBFS/Hz input noise at 185 MHz, 1 dBFS A and 12 D0 IN 12-BIT . ADC 250 MSPS VINA PARALLEL Total power consumption: 770 mW at 250 MSPS VCM AD9613 . DDR LVDS . AND 1.8 V supply voltages VIN+B PIPELINE 12 D11 DRIVERS 12-BIT LVDS (ANSI-644 levels) outputs VINB ADC Integer 1-to-8 input clock divider (625 MHz maximum input) DCO REFERENCE Sample rates of up to 250 MSPS OR IF sampling frequencies of up to 400 MHz 1 TO 8 Internal ADC voltage reference CLOCK SERIAL PORT OEB DIVIDER Flexible analog input range PDWN 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer SCLK SDIO CSB CLK+ CLK SYNC 95 dB channel isolation/crosstalk NOTES 1. THE D0 TO D11 PINS REPRESENT BOTH THE CHANNEL A Serial port control AND CHANNEL B LVDS OUTPUT DATA. Energy-saving power-down modes Figure 1. APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) Programming for setup and control is accomplished using a with sampling speeds of up to 250 MSPS. The AD9613 is designed 3-wire SPI-compatible serial interface. to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. The AD9613 is available in a 64-lead LFCSP and is specified over the industrial temperature range of 40C to +85C. This The dual ADC cores feature a multistage, differential pipelined product is protected by a U.S. patent. architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user- PRODUCT HIGHLIGHTS selectable input ranges. An integrated voltage reference eases design 1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. considerations. A duty cycle stabilizer (DCS) is provided to 2. Fast overrange and threshold detect. compensate for variations in the ADC clock duty cycle, 3. Proprietary differential input maintains excellent SNR allowing the converters to maintain excellent performance. performance for input frequencies of up to 400 MHz. The ADC output data is routed directly to the two external 12-bit 4. SYNC input allows synchronization of multiple devices. LVDS output ports and formatted as either interleaved or channel 5. 3-pin, 1.8 V SPI port for register programming and register multiplexed. readback. 6. Pin compatibility with the AD9643, allowing a simple Flexible power-down options allow significant power savings, migration up to 14 bits, and with the AD6649 and the AD6643. when desired. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 09637-001AD9613 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 23 Applications ....................................................................................... 1 Voltage Reference ....................................................................... 25 General Description ......................................................................... 1 Clock Input Considerations ...................................................... 25 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 27 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 27 Revision History ............................................................................... 2 ADC Overrange (OR) ................................................................ 27 Specifications ..................................................................................... 3 Channel/Chip Synchronization .................................................... 28 ADC DC Specifications ............................................................... 3 Serial Port Interface (SPI) .............................................................. 29 ADC AC Specifications ............................................................... 4 Configuration Using the SPI ..................................................... 29 Digital Specifications ................................................................... 6 Hardware Interface ..................................................................... 29 Switching Specifications .............................................................. 8 SPI Accessible Features .............................................................. 30 Timing Specifications .................................................................. 9 Memory Map .................................................................................. 31 Absolute Maximum Ratings .......................................................... 11 Reading the Memory Map Register Table ............................... 31 Thermal Characteristics ............................................................ 11 Memory Map Register Table ..................................................... 32 ESD Caution ................................................................................ 11 Memory Map Register Description ......................................... 34 Pin Configurations and Function Descriptions ......................... 12 Applications Information .............................................................. 35 Typical Performance Characteristics ........................................... 16 Design Guidelines ...................................................................... 35 Equivalent Circuits ......................................................................... 22 Outline Dimensions ....................................................................... 36 Theory of Operation ...................................................................... 23 Ordering Guide .......................................................................... 36 ADC Architecture ...................................................................... 23 Changes to Output Enable Bar and Power-Down Pin Type REVISION HISTORY and Pin 47 Description .................................................................. 13 2/2017Rev. C to Rev. D Changes to Figure 5 and Pin 7 and Pin 8 Descriptions ............. 14 Changes to Table 9 .......................................................................... 14 Changes to Pin 42 and Pin 43, Output Enable Bar and Power- Down Pin Type, and Pin 47 Descriptions ................................... 15 1/2013Rev. B to Rev. C Changes to Typical Performance Characteristics Conditions .. 16 Changes to Features .......................................................................... 1 Changes to Fiugre 43 ...................................................................... 22 Changes to Table 1 ............................................................................ 3 Added ADC Overrange (OR) Section ......................................... 27 Changes to Table 2 ........................................................................... 5 Changes to Channel/Chip Synchronization Section ................. 28 Change to Logic Inputs (SDIO) Paramter, Table 3....................... 6 Changes to Reading the Memory Map Register Table Changes to Table 4 ............................................................................ 8 Section and Transfer Register Map Section ................................ 31 Change to Reading the Memory Map Register Table Section ....... 31 Changes to Register 0x02, Bits 5:4 .............................................. 32 Changes to Table 14 ........................................................................ 33 Changes to Register 0x16, Bit 5 .................................................... 33 Change to Memory Map Register Description Section............. 34 Added Register 0x3A ..................................................................... 34 Updated Outline Dimensions ....................................................... 36 Deleted Register 0x59 .................................................................... 34 Changes to Bit 0Master Sync Buffer Enable Section ............. 34 9/2011Rev. A to Rev. B Deleted SYNC Pin Control (Register 0x59) Section .................. 34 Changes to Figure 1 .......................................................................... 1 Changes to Temperature Drift Parameters ................................... 3 5/2011Rev. 0 to Rev. A Changes Output Offset Voltage (V ), ANSI Mode Typ OS Changes to Table 2, AD9613-170: Worst Second or Third Parameter and Output Offset Voltage (V ), Reduced Swing OS Harmonic and Worst Other (Harmonic or Spur) Max Values Mode Parameter................................................................................ 7 and Spurious Free Dynamic Range Min Value ............................. 4 Changes DCO to Data Skew (tSKEW) Parameters .......................... 8 4/2011Revision 0: Initial Version Rev. D Page 2 of 36