X-On Electronics has gained recognition as a prominent supplier of ADF4110BRUZ phase locked loops - pll across the USA, India, Europe, Australia, and various other global locations. ADF4110BRUZ phase locked loops - pll are a product manufactured by Analog Devices. We provide cost-effective solutions for phase locked loops - pll, ensuring timely deliveries around the world.

ADF4110BRUZ

ADF4110BRUZ electronic component of Analog Devices
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Part No.ADF4110BRUZ
Manufacturer: Analog Devices
Category:Phase Locked Loops - PLL
Description: Phase Locked Loops - PLL SGL Integer-N 550 MHz
Datasheet: ADF4110BRUZ Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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RF PLL Frequency Synthesizers Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 FEATURES GENERAL DESCRIPTION ADF4110: 550 MHz ADF4111: 1.2 GHz ADF4112: 3.0 GHz The ADF4110 family of frequency synthesizers can be used to ADF4113: 4.0 GHz implement local oscillators in the upconversion and downcon- 2.7 V to 5.5 V power supply version sections of wireless receivers and transmitters. They Separate charge pump supply (VP) allows extended tuning consist of a low noise digital PFD (phase frequency detector), a voltage in 3 V systems precision charge pump, a programmable reference divider, Programmable dual-modulus prescaler 8/9, 16/17, 32/33, programmable A and B counters, and a dual-modulus prescaler 64/65 Programmable charge pump currents (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction Programmable antibacklash pulse width with the dual-modulus prescaler (P/P + 1), implement an N 3-wire serial interface divider (N = BP + A). In addition, the 14-bit reference counter Analog and digital lock detect (R counter) allows selectable REFIN frequencies at the PFD Hardware and software power-down mode input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage APPLICATIONS controlled oscillator (VCO). Base stations for wireless radio (GSM, PCS, DCS, CDMA, WCDMA) Control of all the on-chip registers is via a simple 3-wire Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) interface. The devices operate with a power supply ranging Wireless LANS from 2.7 V to 5.5 V and can be powered down when not in use. Communications test equipment CATV equipment FUNCTIONAL BLOCK DIAGRAM AV DV V R CPGND SET DD DD P REFERENCE 14-BIT REF IN R COUNTER PHASE CHARGE FREQUENCY PUMP CP 14 DETECTOR R COUNTER LATCH CLK 24-BIT FUNCTION DATA LOCK CURRENT CURRENT INPUT REGISTER LATCH 22 DETECT SETTING 1 SETTING 2 LE A, B COUNTER SD LATCH OUT CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 19 FROM HIGH Z FUNCTION LATCH AV DD 13 MUX MUXOUT N = BP + A 13-BIT B COUNTER SD OUT RF A IN LOAD PRESCALER P/P +1 LOAD RF B IN 6-BIT M3 M2 M1 A COUNTER ADF4110/ADF4111 6 ADF4112/ADF4113 CE AGND DGND Figure 1. Functional Block Diagram Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 03496-0-001ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Phase Frequency Detector (PFD) and Charge Pump ............ 13 Applications ....................................................................................... 1 Muxout and Lock Detect ........................................................... 13 General Description ......................................................................... 1 Input Shift Register .................................................................... 13 Functional Block Diagram .............................................................. 1 Function Latch ............................................................................ 19 Revision History ............................................................................... 2 Initialization Latch ..................................................................... 20 Specifications ..................................................................................... 3 Device Programming after Initial Power-Up ......................... 20 Timing Characteristics ..................................................................... 5 Resynchronizing the Prescaler Output .................................... 21 Absolute Maximum Ratings ............................................................ 6 Applications ..................................................................................... 22 Transistor Count ........................................................................... 6 Local Oscillator for GSM Base Station Transmitter .............. 22 ESD Caution .................................................................................. 6 Using a D/A Converter to Drive the RSET Pin ......................... 23 Pin Configurations and Function Descriptions ........................... 7 Shutdown Circuit ....................................................................... 23 Typical Performance Characteristics ............................................. 8 Wideband PLL ............................................................................ 23 Circuit Description ......................................................................... 12 Direct Conversion Modulator .................................................. 25 Reference Input Section ............................................................. 12 Interfacing ................................................................................... 26 RF Input Stage ............................................................................. 12 PCB Design Guidelines for Chip Scale Package .................... 26 Prescaler (P/P + 1) ...................................................................... 12 Outline Dimensions ....................................................................... 27 A and B Counters ....................................................................... 12 Ordering Guide ............................................................................... 28 R Counter .................................................................................... 12 REVISION HISTORY 1/13Rev. E to Rev. F 3/03Data sheet changed from Rev. A to Rev. B. Changes to Table 1 ............................................................................. 4 Edits to Specifications ....................................................................... 2 Changes to Ordering Guide ........................................................... 28 Updated OUTLINE DIMENSIONS ............................................. 24 8/12Rev. D to Rev. E 1/01Data sheet changed from Rev. 0 to Rev. A. Changed CP-20-1 to CP-20-6 ........................................... Universal Changes to DC Specifications in B Version, B Chips, Updated Outline Dimensions ........................................................ 28 Unit, and Test Conditions/Comments Columns ..................... 2 Changes to Ordering Guide ........................................................... 28 Changes to Absolute Maximum Rating ......................................... 4 Changes to FRINA Function Test ..................................................... 5 5/12Rev. C to Rev. D Changes to Figure 8 ........................................................................... 7 Changes to Figure 2 ........................................................................... 5 New Graph AddedTPC 22 ........................................................... 9 Changes to Figure 4 and Table 4 ...................................................... 7 Change to PD Polarity Box in Table V ......................................... 15 Updated Outline Dimensions ........................................................ 28 Change to PD Polarity Box in Table VI ........................................ 16 Changes to Ordering Guide ........................................................... 28 Change to PD Polarity Paragraph ................................................. 17 Addition of New Material 3/04Data sheet changed from Rev. B to Rev. C. (PCB Design Guidelines for ChipScale package) ................ 23 Updated Format .................................................................. Universal Replacement of CP-20 Outline with CP-20 2 Outline ............ 24 Changes to Specifications ................................................................. 2 Changes to Figure 32 ....................................................................... 22 Changes to the Ordering Guide ..................................................... 28 Rev. F Page 2 of 28

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8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
AD4
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DA4
Dallas
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Trinamic
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Trinamic Motion Control GmbH

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