Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs Data Sheet ADRF6720-27 FEATURES GENERAL DESCRIPTION I/Q modulator with integrated fractional-N PLL The ADRF6720-27 is a wideband quadrature modulator with an RF output frequency range: 400 MHz to 3000 MHz integrated synthesizer ideally suited for 3G and 4G com- Internal LO frequency range: 356.25 MHz to 2855 MHz munication systems. The ADRF6720-27 consists of a high Output P1dB: 10.8 dBm at 2140 MHz linearity broadband modulator, an integrated fractional-N Output IP3: 31.1 dBm at 2140 MHz phase-locked loop (PLL), and four low phase noise multicore Carrier feedthrough: 44.3 dBm at 2140 MHz voltage controlled oscillators (VCOs). Sideband suppression: 40.8 dBc at 2140 MHz The ADRF6720-27 local oscillator (LO) signal can be generated Noise floor: 159.5 dBm/Hz at 2140 MHz internally via the on-chip integer-N and fractional-N synthesizers, Baseband 1 dB modulation bandwidth: >1000 MHz or externally via a high frequency, low phase noise LO signal. Baseband input bias level: 2.68 V The internal integrated synthesizer enables LO coverage from Power supply: 3.3 V/425 mA 356.25 MHz to 2855 MHz using the multicore VCOs. In the Integrated RF tunable balun allowing single-ended RF output case of internal LO generation or external LO input, quadrature Multicore integrated VCOs signals are generated with a divide by 2 phase splitter. When the HD3/IP3 optimization ADRF6720-27 is operated with an external 1 LO input, a Sideband suppression and carrier feedthrough optimization polyphase filter generates the quadrature inputs to the mixer. High-side/low-side LO injection The ADRF6720-27 offers digital programmability for carrier Programmable via 3-wire serial port interface (SPI) feedthrough optimization, sideband suppression, HD3/IP3 40-lead 6 mm 6 mm LFCSP optimization, and high-side or low-side LO injection. APPLICATIONS The ADRF6720-27 is fabricated using an advanced silicon- 2G/3G/4G/LTE broadband communication systems germanium BiCMOS process. It is available in a 40-lead, Microwave point-to-point radios RoHS-compliant, 6 mm 6 mm LFCSP package with an Satellite modems exposed pad. Performance is specified over the 40C to +85C Military/aerospace temperature range. Instrumentation FUNCTIONAL BLOCK DIAGRAM VPOSx 40 35 30 26 22 17 11 6 I+ 3 27 ENBL ADRF6720-27 V TO I PHASE 4 I LO NULLING CORRECTION DAC 24 RFOUT LO NULLING DAC PHASE 8 Q CORRECTION V TO I 18 LOOUT+ Q+ 9 19 LOOUT 39 REFIN PLL 36 CP QUAD DIVIDER 32 VTUNE LOIN 33 15 CS LOIN+ 34 SERIAL POLYPHASE LDO LDO 14 PORT SCLK FILTER 2.5V VCO INTERFACE 13 SDIO 2 5 7 10 16 20 23 25 29 37 38 12 31 28 DECL1 DECL2 DECL3 GND Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 12488-001ADRF6720-27 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 LO Input ...................................................................................... 24 Applications ....................................................................................... 1 Loop Filter ................................................................................... 24 General Description ......................................................................... 1 RF Output .................................................................................... 24 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 25 Revision History ............................................................................... 2 DAC to I/Q Modulator Interfacing .......................................... 25 Specifications ..................................................................................... 3 Baseband Bandwidth ................................................................. 26 Timing Characteristics ................................................................ 7 Carrier Feedthrough Nulling .................................................... 26 Absolute Maximum Ratings ............................................................ 8 Sideband Suppression Optimization ....................................... 26 Thermal Resistance ...................................................................... 8 Linearity ....................................................................................... 27 ESD Caution .................................................................................. 8 LO Amplitude and Common-Mode Voltage.......................... 27 Pin Configuration and Function Descriptions ............................. 9 Operating Out of Frequency Range ......................................... 28 Typical Performance Characteristics ........................................... 11 Spurious Performance ............................................................... 28 Theory of Operation ...................................................................... 18 Layout .......................................................................................... 29 LO Generation Block ................................................................. 18 Characterization Setups ................................................................. 30 Baseband ...................................................................................... 21 Register Map ................................................................................... 32 Active Mixers .............................................................................. 21 Register Details ............................................................................... 33 Serial Port Interface .................................................................... 22 Outline Dimensions ....................................................................... 43 Basic Connections for Operation ................................................. 23 Ordering Guide .......................................................................... 43 Power Supply and Grounding ................................................... 23 Baseband Inputs .......................................................................... 24 REVISION HISTORY 9/15Rev. A to Rev. B 3/15Rev. 0 to Rev. A Changed RF = 4 dBm to RF 4 dBm, and USB to Added Spurious Performance Section and Figure 57 to OUT OUT Sideband Suppression ................................................... Throughout Figure 59 Renumbered Sequentially ........................................... 28 Changes to Spurious Performance Section and Figure 59 ........ 28 Added Figure 60 ............................................................................. 29 Changes to Figure 60 ...................................................................... 29 10/14Revision 0: Initial Version Rev. B Page 2 of 43