DS1222 BankSwitch Chip www.dalsemi.com FEATURES PIN ASSIGNMENT Provides bank switching for 16 banks of 1 14 V CEI CC memory 2 13 CEO PFI Bank switching is software-controlled by a 12 pattern recognition sequence on four address BS1 AW 3 CEI 1 16 V CC NC 2 15 CEO inputs AX 4 11 BS2 PFI 3 14 NC Automatically sets all 16 banks off on 10 AY 5 BS3 AW 4 13 BS1 AX 5 12 BS2 power-up AZ 9 BS4 6 AY 6 11 BS3 Bank switching logic allows only one bank on AZ 7 10 NC 8 GND 7 NC GND 8 9 BS4 at a time Custom recognition patterns are available to DS1222 14-Pin DIP DS1222S 16-Pin SOIC prevent unauthorized access (300-mil) (300-mil) See Mech. Drawings See Mech. Drawings Full 10% operating range Section Section Low-power CMOS circuitry Can be used to expand the address range of microprocessors and decoders Optional 16-pin SOIC surface mount package PIN DESCRIPTION A -A - Address Inputs W Z CEI - Chip Enable Input CEO - Chip Enable Output NC - No Connection BS1,BS2, - Bank Select Outputs BS3,BS4 - Bank Select Outputs PFI - Power Fail Input V - +5 Volts CC GND - Ground DESCRIPTION The DS1222 BankSwitch Chip is a CMOS circuit designed to select one of 16 memory banks under software control. Memory bank switching allows for an increase in memory capacity without additional address lines. Continuous blocks of memory are enabled by selecting proper memory bank through a pattern recognition sequence on four address inputs. Custom patterns from Dallas Semiconductor can provide security through uniqueness and prevent unauthorized access. By combining the DS1222 with the DS1212 Nonvolatile Controller x16 Chip, up to 16 banks of static RAMs can be selected. 1 of 4 111899DS1222 OPERATION - BANK SWITCHING Initially, on power-up all four bank select outputs are low and the chip enable output ( CEO ) is held high. (Note: the power fail input PFI must be low prior to power-up to assure proper initialization.) Bank switching is achieved by matching a predefined pattern stored within the DS1222 with a 16-bit sequence received on four address inputs. Prior to entering the 16-bit pattern, which sets the bank switch, a read cycle of 1111 on address inputs AW through AZ should be executed to guarantee that pattern entry starts with bit 0. Each set of address inputs is clocked into the DS1222 when CEI is driven low. All 16 inputs must be consecutive read cycles. The first eleven cycles must match the exact bit pattern as shown in Table 1. The last five cycles must match the exact bit pattern as shown for addresses AX, AY, and AZ. However, address line AW defines the bank number to be enabled as per Table 2. Switching to a selected bank of memory occurs on the rising edge of CEI when the last set of bits is input and a match has been established. After bank selection CEO always follows CEI with a maximum propagation delay of 15 ns. The bank selected is determined by the levels set on Bank Select 1 through Bank Select 4 as per Table 2. These levels are held constant for all memory cycles until a new memory bank is selected. ADDRESS BIT SEQUENCE Table 1 BIT SEQUENCE ADDRESS INPUTS 0123456789 10 11 12 13 14 15 A 10100011010 xxxxx W A 0101110010100011 X A 1010001101011100 Y A 0101110010100011 Z X See Table 2 BANK SELECT CONTROL Table 2 A Bit Sequence Outputs W Bank Selected 11 12 13 14 15 BS1 BS2 BS3 BS4 *Banks Off 0 XX XX Low Low Low Low Bank 0 1 00 00 Low Low Low Low Bank 1 1 00 01 High Low Low Low Bank 2 1 00 10 Low High Low Low Bank 3 1 00 11 High High Low Low Bank 4 1 01 00 Low Low High Low Bank 5 1 01 01 High Low High Low Bank 6 1 01 10 Low High High Low Bank 7 1 0 1 1 1 High High High Low Bank 8 1 10 00 Low Low Low High Bank 9 1 10 01 High Low Low High Bank 10 11 01 0 Low High Low High Bank 11 11 01 1 High High Low High Bank 12 11 10 0 Low Low Low High Bank 13 1 1 1 0 1 High Low High High Bank 14 1 1 1 1 0 Low High High High Bank 15 1 1 1 1 1 High High High High * CEO =V independent of CEI IH 2 of 4