PEX 8724, PCI Express Gen 3 Switch, 24 Lanes, 6 Ports Highlights The ExpressLane PEX 8724 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their PEX 8724 General Features o 24-lane, 6-port PCIe Gen 3 switch respective endpoints via scalable, high bandwidth, non-blocking - Integrated 8.0 GT/s SerDes 2 interconnection to a wide variety of applications including servers, o 19 x 19mm , 324-pin FCBGA package o Typical Power: 5.0 Watts storage, communications, and graphics platforms. The PEX 8724 is well suited for fan-out, aggregation, and peer-to-peer traffic patterns. PEX 8724 Key Features o Standards Compliant Multi-Host Architecture - PCI Express Base Specification, r3.0 The PEX 8724 employs an enhanced version of PLXs field tested PEX 8624 (compatible w/ PCIe r1.0a/1.1 & 2.0) PCIe switch architecture, which allows users to configure the device in legacy - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant single-host mode or multi-host mode with up to four host ports capable of 1+1 - Supports Access Control Services (one active & one backup) or N+1 (N active & one backup) host failover. This - Dynamic link-width control powerful architectural enhancement enables users to build PCIe based systems - Dynamic SerDes speed control to support high-availability, failover, redundant, or clustered systems. o High Performance performancePAK 9 Read Pacing (bandwidth throttling) High Performance & Low Packet Latency 9 Multicast The PEX 8724 architecture supports packet cut-thru with a maximum 9 Dynamic Buffer/FC Credit Pool latency of 106ns (x8 to x8). This, combined with large packet memory, - Non-blocking switch fabric flexible common buffer/FC credit pool and non-blocking internal switch - Full line rate on all ports - Packet Cut-Thru with 106ns max packet architecture, provides full line rate on all ports for performance-hungry latency (x8 to x8) applications such as servers and switch fabrics. The low latency enables - 2KB Max Payload Size applications to achieve high throughput and performance. In addition to low o Flexible Configuration latency, the device supports a packet payload size of up to 2048 bytes, - Ports configurable as x1, x2, x4, x8 enabling the user to achieve even higher throughput. - Registers configurable with strapping 2 pins, EEPROM, I C, or host software - Lane and polarity reversal Data Integrity - Compatible with PCIe 1.0a PM The PEX 8724 provides end-to-end CRC (ECRC) protection and Poison bit o Multi-Host & Fail-Over Support support to enable designs that require end-to-end data integrity. PLX also - Configurable Non-Transparent (NT) port - Failover with NT port supports data path parity and memory (RAM) error correction circuitry - Up to 4 upstream/Host ports with 1+1 or throughout the internal data paths as packets pass through the switch. N+1 failover to other upstream ports o Quality of Service (QoS) Flexible Configuration - Eight traffic classes per port The PEX 8724s 6 ports can be - Weighted round-robin source x4 x8 port arbitration configured to lane widths of x1, o Reliability, Availability, Serviceability x2, x4, or x8. Flexible buffer visionPAK allocation, along with the device s PEPEPEX 8724PEX 8724X 87X 872424 PPEX 8724EX 8724 9 Per Port Performance Monitoring PEX 8724PEX 8724 flexible packet flow control, Per port payload & header counters maximizes throughput for 9 SerDes Eye Capture 9 PCIe Packet Generator applications where more traffic 5 x4 x4 x4 x4 x4 9 Error Injection and Loopback flows in the downstream, rather - 3 Hot Plug Ports with native HP Signals x8 x8 than upstream, direction. Any 2 - All ports hot plug capable thru I C port can be designated as the (Hot Plug Controller on every port) upstream port, which can be - ECRC and Poison bit support PPEX 8724EX 8724 PEPEX 8X 8724724 PEX 8724PEX 8724 PEX 8724PEX 8724 - Data Path parity changed dynamically. Figure 1 - Memory (RAM) Error Correction shows some of the PEX 8724s - INTA and FATAL ERR signals common port configurations in - Advanced Error Reporting x8 x4 x4 x8 x8 legacy Single-Host mode. - Port Status bits and GPIO available Figure 1. Common Port Configurations Per port error diagnostics - JTAG AC/DC boundary scan PLX Technology, www.plxtech.com Page 1 of 5 10/7/2010, Version 1.0 PEX 8724, PCI Express Gen 3 Switch, 24 Lanes, 6 Ports The PEX 8724 can also be configured in Multi-Host mode Multi-Host & Failover Support where users can choose up to four ports as host/upstream In Multi-Host mode, PEX 8724 can be configured with up ports and assign a desired number of downstream ports to to four upstream host ports, each with its own dedicated each host. In Multi-Host mode, a virtual switch is created downstream ports. The device can be configured for 1+1 for each host port and its associated downstream ports redundancy or N+1 redundancy. The PEX 8724 allows the inside the device. The traffic between the ports of a virtual hosts to communicate their status to each other via special switch is completely isolated from the traffic in other door-bell registers. In failover mode, if a host fails, the virtual switches. Figure 2 illustrates some configurations host designated for failover will disable the upstream port of the PEX 8724 in Multi-Host mode where each ellipse attached to the failing host and program the downstream represents a virtual switch inside the device. ports of that host to its own domain. Figure 4a shows a two host system in Multi-Host mode with two virtual switches x4 x4 x8 x4 The PEX 8724 inside the device and Figure 4b shows Host 1 disabled also provides after failure and Host 2 having taken over all of Host 1s several ways to end-points. configure its PEX 87PEX 87PPEX 87EX 8724242424 PEX 8724PEX 8724PPEX 8724EX 8724 Host 1Host 1Host 1Host 1 Host 2Host 2Host 2Host 2 HoHoHoHostststst 1 1 1 1 HosHosHosHost 2t 2t 2t 2 registers. The device can be PEX 87PEX 872424 PEX 87PEX 872424 configured through 2 x4 2 x4 2 x4 2 x2 2 strapping pins, I C x4 x4 x8 x2 interface, host EEEEnd nd nd nd EnEnEnEnd d d d EnEnEnEnd d d d EnEnEnEnd d d d EnEnEnEnd d d d EnEnEnEnd d d d EnEnEnEnd d d d EnEnEnEnd d d d software, or an PoPointint PoPoinintt PoPoinintt PoPointint PoPoinintt PoPointint PoPoiinntt PoPointint PoPointint PoPoinintt PoPoinintt PoPointint PoPoinintt PoPointint PoPoiinntt PoPointint optional serial Figure 4a. Multi-Host Figure 4b. Multi-Host Fail-Over PEX 8724PEX 8724 PEX 8724PEX 8724 EEPROM. This PPEX 8724EX 8724 PPEX 8724EX 8724 Hot Plug for High Availability allows for easy Hot plug capability allows users to replace hardware debug during the 2 x2 2 x2 2 x4 2 x1 modules and perform maintenance without powering down development the system. The PEX 8724 hot plug capability feature Figure 2. Multi-Host Port Configurations phase, makes it suitable for High Availability (HA) performance monitoring during the operation phase, and applications. Three downstream ports include a Standard driver or software upgrade. Hot Plug Controller. If the PEX 8724 is used in an application where one or more of its downstream ports Dual-Host & Failover Support connect to PCI Express slots, each ports Hot Plug In Single-Host mode, the PEX 8724 supports a Non- Controller can be used to manage the hot-plug event of its Transparent (NT) Port, which enables the associated slot. Every port on the PEX 8724 is equipped implementation of PrimPrimaarry Hy Hoostst SeSeccondaondaryry H Hoosstt PPrriimmary Hary Hoosstt SSececoonnddaarry Hy Hoostst with a hot-plug control/status register to support hot-plug dual-host systems for CPUCPU CPUCPU CPUCPU CPUCPU 2 capability through external logic via the I C interface. redundancy and host failover capability. The RoRooott RoRooott SerDes Power and Signal Management NT port allows systems CompComplexlex CompComplexlex The PEX 8724 provides low power capability that is fully to isolate host memory compliant with the PCIe power management specification domains by presenting NT and supports software control of the SerDes outputs to the processor subsystem PEPEX 872X 87244 Non-Transparent allow optimization of power and signal strength in a as an endpoint rather Port system. Furthermore, the SerDes block supports loop-back than another memory EnEnEnd d d EnEnEnd d d EnEnEnddd EnEnEnd d d EnEnEnd d d EnEnEnddd modes and advanced reporting of error conditions, system. Base address PoPoPoinininttt PoPoPoinininttt PoPoPointintint PoPoPoinininttt PoPoPoinininttt PoPoPointintint which enables efficient management of the entire system. registers are used to Figure 3. Non-Transparent Port translate addresses Interoperability doorbell registers are used to send interrupts between the The PEX 8724 is designed to be fully compliant with the address domains and scratchpad registers (accessible by PCI Express Base Specification r2.0, and is backwards both CPUs) allow inter-processor communication (see compatible to PCI Express Base Specification r1.1 and Figure 3). PLX Technology, www.plxtech.com Page 2 of 5 10/7/2010, Version 1.0