AES Encryption IP Security System IP LockIP Lock is FPGA logic security system which used very reliable AES encryption technology. IP propaties in FPGA are protected from illegal copy by only including IP Lock in FPGA and connectiing with encryption controller chip. Features Strong security by AES encryption Encryption controller chip Change & encrypt authentication data at about 200msec cycle Send to Encryption Send controller chip encrypted data Generate true random authentication data by FPGA natural random number generator Power On Reset 128bit data Stop user logic when removing the chip Decryption generation Repeat changing 128bit authentication data Connecting I/O with FPGA are only 2 pins every 200msec No need to input clock to IP Lock logic User logic works Provide easy laboratories pack and IP Lock writer + blank chip IP core Comparison enable Enable signal Match AES Cryptosystem Miss match AES(Advanced Encryption Standard) is common key cryptosystem chosen by NIST, US. Both encryption and Stop decryption are high speed. And it is also stronger than triple DES. So it is noticed as encryption standard for next IP Lock encryption/decryption process flowchart generation replaced with DES. Currently AES is adopted with security for financial system, LAN system and so on. Altera/Xilinx FPGA 1. 128bit data generation real size Enable Encryption Signal User Logic 2. Encryption controller chip Core FPGA and encryption controller chip 3.Decryption/Comparison are connected by 2 I/O only IP Lock block diagramUsage Laboratories pack Laboratories pack containes encryption chips which are already written unique ID at shipment. It is for small usage. IP Lock implementation example Unique ID for each pack written by DesignGateway Step1: IP Lock writer + blank chip SOP8 pin package mount encryption chip IPL-CHP real size User can write any ID to blank chip by using IP Lock writer Step2: Implement IP Lock to FPGA Possible to write optional ID to blank chips by IP Lock writer. Because every IP Lock writer have different ID, even if a user write same key but using different IP Lock writer, written ID are also different. It is for mass production or using it for several products. Specifications IP Lock Production name Cryptosystem AES-128 Cryptosystem Consumption resources of about 1,200LE / about 24,500 memory bit (for Altera FPGA) IP Lock core about 400 slices / 2 blockRAM (for Xilinx FPGA) Encryption controller SOP8 pin package 2 I/O for connecting with FPGA No need clock input Contents IP Lock encryption contrpller chip IP Lock core netlist User s manual ID writing software (for Windows, included in IP Lock writer IPL-003WR only) Part number IP Lock Laboratories pack IPL-010L IP core netlist + encryption controller chip 10pcs pack IPL-030L IP core netlist + encryption controller chip 30pcs pack IP Lock writer IPL-003WR IP Lock writer (with IPL-CHP 3pcs) IPL-CHP Blank chip for IP Lock writer (MOQ 100pcs) 54 BB Building 13th Floor, Room1302, Sukhumvit 21(Asoke), Klongtoey-Nua, Wattana, Bangkok 10110 THAILAND TEL : +66-(0)2-261-2277 www.design-gateway.com FAX : +66-(0)2-261-2290 sales design-gateway.com IPL-LF-V1.2E