ATWINC3400A-MU ATWINC3400A-MU IEEE 802.11 b/g/n Network Controller with Integrated Bluetooth SoC Introduction The Microchip ATWINC3400 is an IEEE 802.11 b/g/n RF/Baseband/Medium Access Control (MAC) network controller with Bluetooth Low Energy. It is Bluetooth 5.0 certified and optimized for low-power and high-performance applications. The ATWINC3400 radio features fully integrated Power Amplifier (PA), Low Noise Amplifier (LNA), Switch, Power Management Unit (PMU) and integrated Flash memory for system software. The ATWINC3400 offers high integration and minimal bill of materials thereby reducing system cost. The ATWINC3400 external clock sources needed are a high-speed crystal or oscillator with 26 MHz, and a 32.768 kHz clock for sleep operation. The ATWINC3400 is available in small, 6*6mm QFN packaging. The ATWINC3400 utilizes highly optimized IEEE 802.11 and Bluetooth coexistence protocols, and provides a Serial Peripheral Interface (SPI) to interface with the host controller. Features Wi-Fi Features: IEEE 802.11 b/g/n with Single Spatial Stream (1x1), 2.4 GHz ISM Band Integrated PA and T/R Switch Superior Sensitivity and Range via Advanced PHY Signal Processing Advanced Equalization and Channel Estimation Advanced Carrier and Timing Synchronization Supports Soft-AP Supports IEEE 802.11 WEP, WPA, and WPA2 Personal and WPA2 Enterprise (firmware v. 1.3.1 or later) Superior MAC Throughput through Hardware Accelerated Two-Level A-MSDU/A-MPDU Frame Aggregation and Block Acknowledgment On-Chip Memory Management Engine to Reduce the Host Load Operating Temperature Range from -40C to +85C SPI Host Interface Integrated Flash Memory for Wi-Fi and Bluetooth System Software Low Leakage On-Chip Memory for State Variables Fast AP Re-Association (150 ms) On-Chip Network Stack to Offload Host MCU Network Features: TCP, UDP, DHCP, ARP, HTTP, TLS, DNS, and SNTP Bluetooth Features: Bluetooth Low Energy 5.0 Adaptive Frequency Hopping (AFH) Superior Sensitivity and Range Datasheet DS70005390A-page 1 2020 Microchip Technology Inc. ATWINC3400A-MU Table of Contents Introduction.....................................................................................................................................................1 Features......................................................................................................................................................... 1 1. Ordering Information and IC Marking......................................................................................................4 2. Functional Overview................................................................................................................................5 2.1. Block Diagram..............................................................................................................................5 2.2. Pinout Information........................................................................................................................ 6 2.3. Pinout Description........................................................................................................................ 6 2.4. Package Description.................................................................................................................... 9 3. Clocking................................................................................................................................................ 10 3.1. Crystal Oscillator........................................................................................................................ 10 3.2. Low-Power Oscillator..................................................................................................................11 4. CPU and Memory Subsystem...............................................................................................................12 4.1. Processor................................................................................................................................... 12 4.2. Memory Subsystem....................................................................................................................12 4.3. Nonvolatile Memory (eFuse)...................................................................................................... 12 5. WLAN Subsystem................................................................................................................................. 14 5.1. MAC........................................................................................................................................... 14 5.1.1. Features.......................................................................................................................14 5.2. PHY............................................................................................................................................15 5.2.1. Features.......................................................................................................................15 6. Bluetooth Low Energy...........................................................................................................................16 7. Radio.....................................................................................................................................................17 7.1. WLAN Transmitter Performance................................................................................................ 17 7.2. WLAN Receiver Performance.................................................................................................... 18 7.3. Bluetooth Transmitter Performance............................................................................................19 7.4. Bluetooth Receiver Performance............................................................................................... 20 8. External Interfaces................................................................................................................................ 21 8.1. Interfacing with the Host Microcontroller.................................................................................... 21 2 8.2. I C Slave Interface..................................................................................................................... 22 2 8.2.1. I C Slave Timing..........................................................................................................22 8.3. SPI Slave Interface.....................................................................................................................23 8.3.1. Overview......................................................................................................................23 8.3.2. SPI Timing................................................................................................................... 23 8.4. UART Interface...........................................................................................................................25 9. Power Management..............................................................................................................................26 9.1. Power Architecture.....................................................................................................................26 9.2. Power Consumption...................................................................................................................27 9.2.1. Description of Device States........................................................................................27 DS70005390A-page 2 Datasheet 2020 Microchip Technology Inc.