ChipWhisperer Embedded Security Analysis Tools Stand-Alone Targets NewAE Technology CW305 Artix FPGA Target NewAE Technology Inc. Product Datasheet newae.com e CW305 iTh s an advanced target for performing power analysis & fault injection attacks against hard- ware cryptographic functions implemented in FPGAs. A custom USB interface chip means you can trivially send and receive data to your FPGA design, while also performing FPGA configuration and adjusting external PLL operating frequencies all from the same interface. ESD protection on all I/O lines allows you to perform glitch insertion safely, and an optional BGA socket is perfect for comparing effects across many physical devices. Product Highlights Shunt resistor for measurement of power consumption of core implemented on FPGA. Default option of no decoupling capacitors mounted leaves high-frequency signals present across shunt. ESD protection reduces possibility of resetting USB interface when inserting EM or voltage faults. Three types of FPGA targets (-A35, -A100, SOCKET) allowing implementation of large cryptographic cores. Custom USB interface provides simple address/data register set leaving you to concentrate on FPGA core, and not on details of the USB Interface protocol. Programmable VCC-INT power supply & external oscillators allow you to control external parameters over USB for validation across voltage and frequency. Ordering Summary NAE-CW305-04--- Decoupling capacitor options Shunt resistor FPGA type Product Links Full Documentation NewAE Technology Inc. Your friendly embedded security arsonist. newae.com Specifications Feature Notes/Range FPGA Supported Artix-7 in FTG256 Package. FPGA Configuration support USB (built in), JTAG (requires external tool), SPI Flash memory. Power Supplies 0.8-1.2V (VCC-INT), 4A, Programmable. 1.8V (VCC-AUX), 1.5A, Fixed. 3.3V (VCC-IO), 2A, Fixed. USB Interface Custom high-speed USB 2.0 firmware running on ARM microcon- troller. USB Functions FPGA configuration, VCC-INT setting, PLL configuration, writing onto data-bus for FPGA. USB Example Languages Python (Linux, Windows, Mac OS-X). USB Supported Language Any that can access libusb DLL (C, C++, VB, etc). Supported Toolchains Xilinx Vivado (All FPGAs), Xilinx ISE (XC7A100T only). PLL Channels 3 separate frequencies. PLL Output Range 1-200 MHz. I/O on Expansion Header 27 GPIO (including 2x differential & 3 clock inputs on FPGA). I/O on 20-pin Header 11 GPIO (including 1 clock input on FPGA). I/O on SMA Connectors 2 GPIO (including 1 clock inputs on FPGA). Detailed Ordering Options Code Shunt Notes 0.1 100 mOhm Default & recommended value for most uses. Revision (04) Revision normally 0.0 0 mOhm Useful for EM probe mea- omitted from or - (jumper) surements or PUF usage. dering codes. Shunt value (ohms) NAE-CW305-04-7A35-0.10-X Code FPGA Notes Code PDN Notes 7A35 XC7A35T- Suitable for most symmetric cryp- X No VCC-INT The decoupling capacitors 2FTG256 tographic implementations (i.e., Capacitors on the VCC-INT network are pipelined AES will fit). Must use NOT present. This option Vivado toolchain (ISE only sup- is required if performing ports the XC7A100T). side-channel power analysis using the current shunt. 7A100 XC7A100T- Large FPGA with 3x logic resourc- 2FTG256 es of 7A35. Suitable for very large M VCC-INT The decoupling capacitors crypto implementations. Can use Capacitors on the VCC-INT network are either ISE or Vivado. present. Generally if using the board primarily for PUF SOCKET BGA socket No FPGA provided in socket, analysis or fault injection, with heatsink. supports any Artix-7 in FTG256 this option is suitable. package. Perfect for comparison between devices, such as for PUFs or template attacks. CW305 Datasheet 2 Last Update: 2018-FEB-06