74HCT163D,653

74HC163 74HCT163 Presettable synchronous 4-bit binary counter synchronous reset Rev. 5 12 October 2018 Product data sheet 1. General description The 74HC163 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula: 2. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC163: CMOS level For 74HCT163: TTL level Synchronous counting and loading 2 count enable inputs for n-bit cascading Synchronous reset Positive-edge triggered clock ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC163D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT163DNexperia 74HC163 74HCT163 Presettable synchronous 4-bit binary counter synchronous reset Type number Package Temperature range Name Description Version 74HC163DB -40 C to +125 C SSOP16 plastic shrink small outline package SOT338-1 16 leads body width 5.3 mm 74HCT163DB 74HC163PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mm 74HCT163PW 4. Functional diagram 3 4 5 6 D0 D1 D2 D3 9 3 4 5 6 9 PE PARALLEL PE D0 D1 D2 D3 1 MR LOAD CIRCUITRY 7 CEP 10 CET 10 CET TC 15 2 CP 7 CEP D TC 15 1 MR INH BINARY Q0 Q1 Q2 Q3 2 CP COUNTER CP Q0 Q1 Q2 Q3 14 13 12 11 aaa-012184 14 13 12 11 aaa-012186 Fig. 1. Logic symbol Fig. 2. Functional diagram CTR4 1 2R 9 M1 7 G3 10 G4 2 C2/1,3,4+ 14 3 1,2D 13 4 12 5 6 11 15 4CT = 15 aaa-012185 Fig. 3. IEC logic symbol 74HC HCT163 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 12 October 2018 2 / 20