74HCT273PW,112

74HC273 74HCT273 Octal D-type flip-flop with reset positive-edge trigger Rev. 7 6 September 2021 Product data sheet 1. General description The 74HC273 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC273: CMOS level For 74HCT273: TTL level Common clock and master reset Eight positive edge-triggered D-type flip-flops ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC273D -40 C to +125 C SO20 plastic small outline package 20 leads body width 7.5 mm SOT163-1 74HCT273D 74HC273PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74HCT273PW 74HC273BQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals 74HCT273BQ body 2.5 4.5 0.85 mmNexperia 74HC273 74HCT273 Octal D-type flip-flop with reset positive-edge trigger 4. Functional diagram 11 CP C1 1 R MR 11 3 2 1D CP D0 Q0 D0 Q0 3 2 3 2 D0 Q0 D1 Q1 4 5 4 5 D1 Q1 4 5 D2 Q2 D1 Q1 7 6 7 6 7 6 D2 Q2 D3 Q3 FF1 D2 Q2 8 9 D4 TO Q4 8 9 8 9 D3 Q3 13 12 D3 Q3 FF8 Q5 D5 13 12 14 15 13 12 D4 Q4 D4 Q4 D6 Q6 14 15 17 16 14 15 D5 Q5 D7 Q7 D5 Q5 18 19 17 16 D6 Q6 17 16 MR D6 Q6 18 19 1 D7 Q7 CP 18 19 MR 11 D7 Q7 1 001aae055 mna763 mna764 Fig. 1. Functional diagram Fig. 2. Logic symbol Fig. 3. IEC logic symbol D0 D1 D2 D3 D Q D Q D Q D Q CP CP CP CP FF1 FF2 FF3 FF4 R R R R D D D D CP MR Q0 Q1 Q2 Q3 D4 D5 D6 D7 D Q D Q D Q D Q CP CP CP CP FF5 FF6 FF7 FF8 R R R R D D D D Q4 Q5 Q6 Q7 001aae056 Fig. 4. Logic diagram 74HC HCT273 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 7 6 September 2021 2 / 17