74LVC2G53GT,115 Nexperia

74LVC2G53 2-channel analog multiplexer/demultiplexer Rev. 14 22 April 2021 Product data sheet 1. General description The 74LVC2G53 is a single-pole double-throw analog switch with a digital select input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and a digital enable input (E). When E is HIGH, the switch is turned off. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt trigger action at the select and enable inputs makes the circuit tolerant of slower input rise and fall times across the entire V range from 1.65 V to 5.5 V. CC 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Very low ON resistance: 7.5 (typical) at V = 2.7 V CC 6.5 (typical) at V = 3.3 V CC 6 (typical) at V = 5 V CC Switch current capability of 32 mA High noise immunity CMOS low-power consumption Overvoltage tolerant inputs to 5.5 V TTL interface compatibility at 3.3 V Latch-up performance meets requirements of JESD 78 Class I ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G53DP -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74LVC2G53DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74LVC2G53GT -40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mm 74LVC2G53GN -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74LVC2G53GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mmNexperia 74LVC2G53 2-channel analog multiplexer/demultiplexer 4. Marking Table 2. Marking codes Type number Marking code 1 74LVC2G53DP V53 74LVC2G53DC V53 74LVC2G53GT V53 74LVC2G53GN V3 74LVC2G53GS V3 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y0 S Z Y1 S Y0 Z Y1 E E 001aad387 001aah795 Fig. 1. Logic symbol Fig. 2. Logic diagram 6. Pinning information 6.1. Pinning 74LVC2G53 Z 1 8 V CC E 2 7 Y0 74LVC2G53 GND 3 6 Y1 Z 1 8 V CC E 2 7 Y0 GND 4 5 S GND 3 6 Y1 GND 4 5 S 001aae800 001aae798 Transparent top view Fig. 3. Pin configuration SOT505-2 (TSSOP8) and Fig. 4. Pin configuration SOT833-1, SOT1116 and SOT765-1 (VSSOP8) SOT1203 (XSON8) 74LVC2G53 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 14 22 April 2021 2 / 23