74HC4024N,652

74HC4024 7-stage binary ripple counter Rev. 9 28 April 2016 Product data sheet 1. General description The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Low-power dissipation Complies with JEDEC standard no. 7A CMOS input levels ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. Multiple package options Specified from 40 Cto+80 C and from 40 Cto+125 C. 3. Applications Frequency dividing circuits Time delay circuits.74HC4024 Nexperia 7-stage binary ripple counter 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4024D 40 C to +125 C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74HC4024PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; SOT402-1 14 leads; body width 4.4 mm 5. Functional diagram    67$*(                                    Fig 1. Logic symbol Fig 2. Functional diagram Fig 3. IEC logic symbol 4 4 4 4 4 4 4  ))  )) ))  ))          7 7 7 7 7 7 7 4 4 4 4 4 4 4 05 4  4   Fig 4. Logic diagram 74HC4024 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 9 28 April 2016 2 of 17 DDE 4 4 4 4 4 5' 5' 5' 5' 5' 5' 5' &3 )) )) )) DDE DDE DDE 4 05 &3 4 &7 4 05 &7 4 4 4 4 &3 4 4 4 5 &7 4 &2817(5 4 4 4