CBTL05023BS,118

CBTL05023 Multiplexer/demultiplexer switch for Thunderbolt applications Rev. 5 15 July 2013 Product data sheet 1. General description The CBTL05023 is a multiplexer/demultiplexer switch chip for DisplayPort v1.2 signals and the control signals of a 10 Gbit/s channel. The 10 Gbit/s channel does not pass through this switch. This chip provides BIASOUT output control signal, and the DC-biasing pull-down resistors to facilitate an external 10 Gbit/s channel. The AUX MUX is a 2 : 1 switch with CA DETect pin selecting between AUX and DDC (Direct Display Control) signals. The DP MUX is a 2 : 1 switch that selects between DPML (DisplayPort Main Link) and LSTX/LSRX signals. This chip also includes three control signal buffers: HPDOUT, CA DETOUT and BIASOUT. CBTL05023 is powered by a 3.3 V supply and it is available in 3 mm 3 mm HVQFN24 package with 0.4 mm pitch. 2. Features and benefits 2.1 AUX MUX 2 : 1 switch This 2 : 1 switch is controlled by CA DET signal multiplexing of the 1 Mbit/s differential AUX and DDC (Direct Display Control) signals When CA DET is HIGH, DDC path is selected Differential AUX channel: Low insertion loss: 0.5 dB at 5 MHz Low return loss: 19 dB at 5 MHz Low ON-state resistance: 7.5 Bandwidth: 5 GHz Low off-state isolation: 75 dB at 5 MHz Low crosstalk: 40 dB at 5 MHz Common-mode input voltage V : 0 V to 3.3 V IC Differential input voltage V : 1.4 V (maximum) ID 2 DDC channel has DDC CLK and DDC DAT I C signals 100 kHz 3.3 V voltage swing Both AUXIO+ and AUXIO outputs have 900 ( 20 %) pull-down resistor that is enabled by the status of the BIASOUT output pin These pull-down resistors provide DC bias for the 10 Gbit/s channelCBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 2.2 DP MUX 2 : 1 switch The DP MUX is a 2:1 switch that is controlled by DP PD pin multiplexing of a differential DPML signal and LSTX/LSRX signals The DPML (DisplayPort Main Link) runs up to HBR2 data rate of 5.4 Gbit/s The low speed DC coupled signals LSTX and LSRX are 3.3 V single-ended signals that operated at 1 Mbit/s 5.4 Gbit/s DPML channel: Low insertion loss for DP-DPMLO path: 2.0 dB at 2.5 GHz Low insertion loss for LS-DPMLO path: 2.0 dB at 2.5 GHz Low return loss for DP-DPMLO path: 15 dB at 2.5 GHz Low return loss for LS-DPMLO path: 14 dB at 2.5 GHz Low ON-state resistance for DP-DPMLO path: 9 Low ON-state resistance for LS-DPMLO path: 13 High bandwidth: 7 GHz Low off-state isolation: 20 dB at 2.5 GHz Low crosstalk: 25 dB at 2.5 GHz Common-mode input voltage V : 0 V to 3.3 V IC Differential input voltage V : 1.4 V (maximum) ID 2.3 General The input of the HPDOUT (Hot Plug Detect output) buffer is 5 V tolerant HPDOUT, CA DETOUT and BIASOUT buffers CA DET input leakage current < 0.1 A to prevent driving the 1 M pull-down to a HIGH level BIASOUT buffer is able to provide enough current to drive the bias circuit for the PIN diode path BIASOUT buffer can drive up to six sets of bias circuits for the 10 Gbit/s paths When AUXIO EN is LOW or (BIASIN = 0 and DP PD = 1), this chip is in Sleep mode AUXIO+ and AUXIO of AUX MUX are disabled CA DETOUT and HPDOUT buffers are on When the chip is in Sleep mode, CBTL05023 consumes < 3.5 mW Patent-pending high-bandwidth analog pass-gate technology Very low intra-pair differential skew (5 ps typical) All channels have back current protection All channels support rail-to-rail input voltage CMOS input buffer with hysteresis Single 3.3 V 10 % power supply HVQFN24 3 mm 3 mm package, 0.4 mm pitch, with exposed center pad for thermal relief and electrical ground ESD: 2500 V HBM, 1250 V CDM Operating temperature range: 0 C to 85 C CBTL05023 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 15 July 2013 2 of 19