MC10EP195FAG ON Semiconductor

MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. EN D1 D1 EN CASCADE D2 D2 CASCADE CASCADE D3 D3 CASCADE V CC V EE V V EE CC SETMAX D4 D4 SETMAX SETMIN D5 D5 SETMIN LEN D6 D6 LEN V EE D7 D7 V EE MC10EP195, MC100EP195 32 31 30 29 28 27 26 25 24 D8 1 V EE 23 D9 2 D0 22 D10 3 V CC 21 Q IN 4 MC10EP195 MC100EP195 20 IN 5 Q 19 V V 6 CC BB 18 V V EF 7 CC 17 V NC 8 CF 9 10 11 12 13 14 15 16 Figure 1. 32Lead LQFP Pinout (Top View) 32 31 30 29 28 27 26 25 1 24 V EE D8 2 23 D0 D9 3 22 V D10 CC 4 21 Q IN 5 20 Q IN V 6 19 CC V BB V 7 18 CC V EF 8 17 NC V CF 9 10 11 12 1314 1516 Exposed Pad (EP) Figure 2. 32Lead QFN (Top View)