Product Information

P1P8160AG-10CR

P1P8160AG-10CR electronic component of ON Semiconductor

Datasheet
Clock Synthesizer / Jitter Cleaner 3.3V LOW JITTER CG

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - WHS 1

MOQ : 1
Multiples : 1

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P1P8160AG-10CR
ON Semiconductor

1 : USD 1.7234
10 : USD 0.8385
100 : USD 0.5113
500 : USD 0.4655
1000 : USD 0.4079
2500 : USD 0.388
10000 : USD 0.383
25000 : USD 0.3701
50000 : USD 0.3591
N/A

Obsolete
     
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RoHS - XON
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Mxhts
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P1P8160A Low Jitter Clock Generator and Peak EMI Reduction IC Product Description P1P8160A is a versatile low jitter clock generator and spread spectrum frequency modulator designed to reduce electromagnetic P1P8160A SS1% SS2% VDD1 VDD2 ModOUT CLKIN/XIN Crystal PLL Oscillator XOUT RefOUT 2 VSS Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin Pin Name Type Description 1 CLKIN / XIN I Crystal connection or External Reference Clock Input. 2 VSS P Ground to entire chip 3 SS2% I Frequency Deviation Selection. Tri level logic pin. Has an internal pull down resistor. Refer to Frequency Deviation Selection table 4 VDD1 Supply Voltage for 100 MHz ModOUT 5 ModOUT O Buffered 100MHz spread spectrum clock output 6 VSS P Ground to entire chip 7 SS1% I Frequency Deviation Selection. Tri level logic pin. Has an internal pull down resistor. Refer to Frequency Deviation Selection table 8 VDD2 P Supply Voltage for 27 MHz RefOUT 9 RefOUT O Buffered reference clock output 10 XOUT O Crystal connection. If using an external reference, this pin must be left unconnected. 3 Level Digital Logic Logic Control Pins SS1% and SS2% digital inputs are designed to sense 3 different logic levels designated as High 1, Low 0 and VDD Middle M. With this 3Level digital inputs, 9 different 1 SS1%, SS2% to V DD logic states can be detected. Use 5k/5k resistor divider at SS1% and SS2% pins from VDD V to V to obtain V /2, Middle M logic level as DD SS DD 5k shown: M SS1%, SS2% 5k VSS SS1%, SS2% to V SS 0 (UNCONNECTED) VSS

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
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ON SEMI
ON Semicon
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ON4
ON5
onsemi
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onsemi / Fairchild
OOF
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