QuickLogic PolarPro 3 Device Data Sheet Ultra-Low Power FPGA Combining Efficient Logic Cells with Embedded RAM and FIFO Blocks to Maximize Logic Density in Minimal PCB Space Embedded Standard Blocks Device Highlights Built in SRAM and FIFO controllers Enables data buffering and autonomous data Ultra Low Power transfers 55 A static power consumption, suitable for smartphones, tablets, mobile enterprise devices Fast Time-to-Market and other power sensitive applications QuickLogic designs and delivers complete Prolongs device battery life Customer Specific Standard Product (CSSP) Small Form Factor Packaging solutions, including hardware and software Uses QuickLogics existing library of Proven 640 and 1,019 logic cell packages as small as System Blocks (PSBs) 2.09 mm x 2.54 mm Reduces development time and costs WLCSP, VFBGA, or die options available Designed for the most space-sensitive Figure 1: PolarPro 3 Block Diagram applications Complete Customizable GPIO GPIO GPIO GPIO Solutions Embedded RAM Blocks Allows offloading of computationally intensive applications FIFO Controller Includes comprehensive software packages along with hardware Efficient Logic Utilization Configurable Logic Flexible logic cells, capable of two independent 3-input LUTs or a single 4-input LUT. FIFO Controller Allows greater functionality in less PCB space Embedded RAM Blocks GPIO GPIO GPIO GPIO 2015 QuickLogic Corporation www.quicklogic.com 1 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO QuickLogic PolarPro 3 Device Data Sheet Rev. 1.2 Flexible Reconfigurable Logic 1.2 V core voltage, 1.8/2.5/3.3 V drive capable I/Os Up to 64 kilobits of SRAM 55 A standby current Up to 46 I/Os available 640 and 1,019 logic cell options Reconfigurable SRAM technology Embedded Dual-Port SRAM Up to eight dual-port 8-kilobit high performance SRAM blocks True dual-port capability Embedded synchronous/asynchronous FIFO controllers Configurable and cascadable aspect ratio Configurable I/O Configurable dual drive strength per GPIO Independent I/O banks capable of supporting multiple I/O standards in one device Bank programmable I/O standards: LVTTL, LVCMOS25 and LVCMOS18 Week pulldown capability and input enables Advanced Clock Network Multiple low skew clock networks 5 programmable global clock networks Quadrant-based segmentable clock networks 20 quad clock networks per device www.quicklogic.com 2015 QuickLogic Corporation 2