IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS IDT74LVC16827A 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: Typical tSK(o) (Output Skew) < 250ps This 20-bit buffer is built using advanced dual metal CMOS technology. ESD > 2000V per MIL-STD-883, Method 3015 > 200V using The LVC16827A provides high-performance bus interface buffering for machine model (C = 200pF, R = 0) wide data/address paths or buses carrying parity. Two pairs of NAND-ed VCC = 3.3V 0.3V, Normal Range output enable controls offer maximum control flexibility and are organized VCC = 2.7V to 3.6V, Extended Range to operate the device as two 10-bit buffers or one 20-bit buffer. Flow-through CMOS power levels (0.4 W typ. static) organization of signal pins simplifies layout. All inputs are designed with All inputs, outputs, and I/O are 5V tolerant hysteresis for improved noise margin. Supports hot insertion The LVC16827A buffer is ideally suited for driving high capacitance loads Available in TSSOP package and low impedance backplanes. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of the device as a translator in a mixed 3.3V/5V supply system. DRIVE FEATURES: The LVC16827A has been designed with a 24mA output driver. The High Output Drivers: 24mA driver is capable of driving a moderate to heavy load while maintaining Reduced system switching noise speed performance. APPLICATIONS: 5V and 3.3V mixed voltage systems Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1 28 1OE1 2OE1 56 29 1OE2 2OE2 42 15 55 2 2Y1 1Y1 1A1 2A1 TO NINE OTHER CHANNELS TO NINE OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE AUGUST 2015 1 2015 Integrated Device Technology, Inc. DSC-4489/6IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND 0.5 to +6.5 V 1OE1 1 56 1OE2 TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 50 to +50 mA 2 1Y1 55 1A1 IIK Continuous Clamp Current, 50 mA 3 54 1Y2 1A2 IOK VI < 0 or VO < 0 ICC Continuous Current through each 100 mA GND 4 53 GND ISS VCC or GND 5 1Y3 52 1A3 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 6 1Y4 1A4 51 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational VCC 7 50 VCC sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 8 1Y5 49 1A5 9 48 1Y6 1A6 10 1Y7 47 1A7 CAPACITANCE (TA = +25C, F = 1.0MHz) 11 46 (1) GND GND Symbol Parameter Conditions Typ. Max. Unit 12 CIN Input Capacitance VIN = 0V 4.5 6 pF 1Y8 45 1A8 COUT Output Capacitance VOUT = 0V 6.5 8 pF 13 1Y9 44 1A9 CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 1Y10 14 43 1A10 NOTE: 1. As applicable to the device type. 15 42 2Y1 2A1 2Y2 16 2A2 41 2Y3 17 40 2A3 PIN DESCRIPTION 18 GND 39 GND Pin Names Description 19 38 2Y4 2A4 xOE x Output Enable Inputs (Active LOW) 20 37 2A5 2Y5 x A x Data Inputs 2Y6 21 36 2A6 x Y x 3-State Outputs 22 35 VCC VCC 23 2Y7 34 2A7 24 33 2Y8 2A8 GND 25 32 (1) GND FUNCTION TABLE 2Y9 26 Inputs Outputs 31 2A9 xOE1 xOE2 xAx xYx 27 2Y10 30 2A10 LL L L 28 29 2OE2 2OE1 LL H H HX X Z XH X Z TSSOP NOTE: TOP VIEW 1. H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care Z = High Impedance 2