DATASHEET
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBF32868A
occurred on the open-drain QERR pin (active low). The
Description
convention is even parity, i.e., valid parity is defined as an
even number of ones across the DIMM-independent data
This 28-bit 1:2 configurable registered buffer is designed for
inputs combined with the parity input bit. To calculate parity,
1.7V to 1.9V VDD operation. All inputs are compatible with
all DIMM-independent D-inputs must be tied to a known
the JEDEC standard for SSTL_18, except the chip-select
logic state. If an error occurs and the QERR output is driven
gate-enable (CSGEN), control (C), and reset (RESET)
low, it stays latched low for a minimum of two clock cycles or
inputs, which are LVCMOS. All outputs are edge-controlled
until RESET is driven low. If two or more consecutive parity
circuits optimized for unterminated DIMM loads, and meet
errors occur, the QERR output is driven low and latched low
SSTL_18 specifications, except the open-drain error
for a clock duration equal to the parity error duration or until
(QERR) output.
RESET is driven low. If a parity error occurs on the clock
The IDT74SSTUBF32868A operates from a differential
cycle before the device enters the low-power (LPM) and the
clock (CLK and CLK). Data are registered at the crossing of
QERR output is driven low, then it stays lateched low for the
CLK going high and CLK going low. The device supports
LPM duration plus two clock cycles or until RESET is driven
low-power standby operation. When RESET is low, the
low. The DIMM-dependent signals (DCKE0, DCKE1,
differential input receivers are disabled, and undriven
DODT0, DODT1, DCS0 and DCS1) are not included in the
(floating) data, clock, and reference voltage (Vref) inputs
parity check computation.
are allowed. In addition, when RESET is low, all registers
The C input controls the pinout configuration from
are reset and all outputs are forced low except QERR. The
register-A configuration (when low) to register-B
LVCMOS RESET and C inputs must always be held at a
configuration (when high). The C input should not be
valid logic high or low level. To ensure defined outputs from
switched during normal operation. It should be hardwired to
the register before a stable clock has been supplied,
a valid low or high level to configure the register in the
RESET must be held in the low state during power up. In
desired mode. The device also supports low-power active
the DDR2 RDIMM application, RESET is specified to be
operation by monitoring both system chip select (DCS0 and
completely asynchronous with respect to CLK and CLK.
DCS1) and CSGEN inputs and will gate the Qn outputs
Therefore, no timing relationship can be ensured between
from changing states when CSGEN, DCS0, and DCS1
the two. When entering reset, the register will be cleared
inputs are high. If CSGEN, DCS0 orDCS1 input is low, the
and the data outputs will be driven low quickly, relative to
Qn outputs will function normally. Also, if both DCS0 and
the time to disable the differential input receivers. However,
DCS1 inputs are high, the device will gate the QERR output
when coming out of reset, the register will become active
from changing states. If either DCS0 orDCS1 is low, the
quickly, relative to the time to enable the differential input
QERR output will function normally. The RESET input has
receivers. As long as the data inputs are low, and the clock
priority over the DCS0 and DCS1 control and when driven
is stable during the time from the low-to-high transition of
low will force the Qn outputs low, and the QERR output
RESET until the input receivers are fully enabled, the
high. If the chip-select control functionality is not desired,
design of the IDT74SSTUBF32868A must ensure that the
then the CSGEN input can be hard-wired to ground, in
outputs will remain low, thus ensuring no glitches on the
which case, the setup-time requirement for DCS0 and
output.
DCS1 would be the same as for the other D data inputs. To
The IDT74SSTUBF32868A includes a parity checking
control the low-power mode with DCS0 and DCS1 only,
function. Parity, which arrives one cycle after the data input
then the CSGEN input should be pulled up to Vdd through a
to which it applies, is checked on the PAR_IN input of the
pullup resistor. The two VREF pins (A1 and V1) are
device. The corresponding QERR output signal for the data
connected together internally by approximately 150.
inputs is generated two clock cycles after the data, to which
However, it is necessary to connect only one of the two
the QERR signal applies, is registered. The
VREF pins to the external VREF power supply. An unused
IDT74SSTUBF32868A accepts a parity bit from the
VREF pin should be terminated with a VREF coupling
memory controller on the parity bit (PAR_IN) input,
capacitor.
compares it with the data received on the
DIMM-independent D-inputs (D1-D5, D7, D9-D12,
D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28
when C = 1) and indicates whether a parity error has
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 1 IDT74SSTUBF32868A 7068/12IDT74SSTUBF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE
Features Applications
28-bit 1:2 registered buffer with parity check functionality DDR2 Memory Modules
Supports SSTL_18 JEDEC specification on data inputs Provides complete DDR DIMM solution with
and outputs ICS98ULPA877A or IDTCSPUA877A
Supports LVCMOS switching levels on CSGEN and Ideal for DDR2 667 and 800
RESET inputs
Low voltage operation: VDD = 1.7V to 1.9V
Available in 176-ball LFBGA package
Block Diagram
M2
RESET
L1
CLK
M1
CLK
A5, AB5
VREF
DCKE0, D1, C1
QCKE0A,
2 F2, E2
DCKE1
D QCKE1A
2
2
CK Q
H8, F8 QCKE0B,
R
QCKE1B
DODT0, N1, P1
N2, P2 QODT0A,
2
DODT1
D
QODT1A
2
2
CK Q
M7, M8
R QODT0B,
QODT1B
K1
DCS0 K2
QCS0A
D
CK Q
R L7
QCS0B
L2
CSGEN
J1
DCS1
J2
QCS1A
D
CK Q
R
L8
QCS1B
One of 22 Channels
A2
D1
A7
CE
D Q1A
CK Q
R A8
Q1B
TO 21 OTHER CHANNELS
(D2-D5, D7, D9-D12, D17-D28)
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 2 IDT74SSTUBF32868A 7068/12