DATASHEET Embedded 56-pin Industrial Temperature ICS9ERS3125 Range CK505 Compatible Clock Recommended Application: Features/Benefits: Industrial temperature CK505-compatible clock Fully integrated Vreg Differential outputs have integrated series resistors to give ZO = 50 Ohms Output Features: Supports spread spectrum modulation, 0 to -0.5% down 2 - CPU differential push-pull pairs spread 4 - SRC differential push-pull pairs Supports CPU clks up to 400MHz 1 - CPU/SRC selectable differential push-pull pair Uses external 14.318MHz crystal, external crystal load 1 - DOT96/SRC selectable differential push-pull pair caps are required for frequency tuning 1 - 27M/SRC/SE selectable pair 1 - SRC/SATA selectable differential push-pull pair Table 1: CPU Frequency Select Table 5 - PCI, 33MHz 2 1 1 1 - PCI F 33MHz free running CPU SRC PCI REF USB DOT FS C FS B FS A L L L MHz MHz MHz MHz MHz MHz B0b7 B0b6 B0b5 1 - USB, 48MHz 0 0 0 266.66 1 - REF, 14.31818MHz 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 100.00 33.33 14.318 48.00 96.00 Key Specifications: 1 0 0 333.33 CPU outputs cycle-cycle jitter < 85ps 1 0 1 100.00 1 1 0 400.00 SRC output cycle-cycle jitter < 125ps 11 1 Reserved PCI outputs cycle-cycle jitter < 250ps 1. FS A and FS B are low-threshold inputs.Please see V and V specifications in L L IL FS IH FS +/- 100ppm frequency accuracy on all outputs the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS C is a three-level input. Please see the V and V L IL FS IH FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Pin Configuration 27 SEL pin19 pin20 0 (B1b7=1) DOT96T DOT96C 1 (B1b7=0) SRCT0 SRCC0 27 SEL pin23 pin24 0 LCDT SS LCDC SS 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 27FIX 27SS X2 GNDSRC 142 X1241 VDDSRC NOTE: Pin 23/24 defaults to a different spread domain than VDDREF PCI STOP 340 SRC without BIOS intervention. REF0/FSLC/TEST SEL CPU STOP 439 SDATA538VDDSRC IO SCLK 6 37 SRCT11/CR H CR SEL PCI0/CR A 7 36 SRCC11/CR G 9ERS3125 VDDPCI835 GNDSRC CR Control Table PCIEX pair control 0 1 PCI1/CR B SRCC4 934 CR A SRC0 or SRC2 SRC0 SRC2 PCI2/TME 10 33 SRCT4 CR B SRC1 or SRC4 SRC1 SRC4 PCI3 11 32 VDDSRCI/O CR C SRC0 or SRC2 SRC0 SRC2 SRCC3/CR D PCI4/27 SEL 12 31 CR D SRC1 or SRC4 SRC1 SRC4 PCI F5/ITP EN 13 30 SRCT3/CR C CR E SRC6 - - GNDPCI GNDSRC 14 29 CR F SRC8 - - 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CR G N/A - - CR H N/A - - 56-pin MLF 8x8mm body TM TM IDT /ICS Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock 161208/19/09 1 VDD48 GNDREF USB 48MHz/FSLA FSLB/TEST MODE GND48 CK PWRGD/PD VDDI/O96Mhz VDDCPU DOTT 96/SRCT0 CPUT0 DOTC 96/SRCC0 CPUC0 GND GNDCPU VDD CPUT1 27FIX/LCDT/SRCT1/SE1 CPUC1 27SS/LCDC/SRCC1/SE2 VDDCPUI/O GND CPUT2 ITP/SRCT8 VDDPLL3I/O CPUC2 ITP/SRCC8 SRCT2/SATAT SRCT7/CR F SRCC2/SATAC SRCT7/CR FICS9ERS3125 Datasheet Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock Pin Description PIN PIN NAME TYPE DESCRIPTION 1 X2 OUT Crystal output, nominally 14.318MHz. 2 X1 IN Crystal input, Nominally 14.318MHz. 3 VDDREF PWR Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency 4 REF0/FSLC/TEST SEL I/O selection. Refer to input electrical characteristics for Vil FS and Vih FS values/ TEST SEL: 3- level latched input to enable test mode. Refer to Test Clarification Table. 5 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 6 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR A EN bit located in byte 5 of SMBUs address space. 7 PCI0/CR A I/O Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR A enabled. Byte 5, bit 6 controls whether CR A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR A controls SRC0 pair (default), 1= CR A controls SRC2 pair 8 VDDPCI PWR Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR B EN bit located in byte 5 of SMBUs address space. 9 PCI1/CR B I/O Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR B enabled. Byte 5, bit 4 controls whether CR B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR B controls SRC1 pair (default) 1= CR B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 10 PCI2/TME I/O 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 11 PCI3 OUT 3.3V PCI clock output. 3.3V PCI clock output / 27MHz mode select for pin23, 24 strap. On powerup, the logic value 12 PCI4/27 SEL I/O on this pin determines the power-up default of DOT 96/SRC0 and 27MHz/LCD/SRC1 output and the function table for the pin23 and pin24. Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI STOP pin. On powerup, the state of this pin determines whether pins 45 13 PCI F5/ITP EN I/O and 46 are an ITP or SRC pair. 0 =SRC8/SRC8 1 = ITP/ITP 14 GNDPCI PWR Ground for PCI clocks. 15 VDD48 PWR Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer 16 USB 48MHz/FSLA I/O to input electrical characteristics for Vil FS and Vih FS values. 17 GND48 PWR Ground pin for the 48MHz outputs. 18 VDD96 IO PWR Power supply for DOT96 output. 1.05 to 3.3V +/-5%. True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 19 DOTT 96/SRCT0 OUT 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0 . After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows 20 DOTC 96/SRCC0 OUT 0= SRC0 1=DOT96 TM TM IDT /ICS Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock 161208/19/09 2