DATASHEET ISL22346WM FN6624 2 Rev 1.00 Quad Digitally Controlled Potentiometers (XDCP) Low Noise, Low Power I C November 11, 2011 Bus, 128 Taps The ISL22346WMVEP integrates four digitally controlled Features potentiometers (DCP) and non-volatile memory on a Specifications per DSCC VID V62/08605-01XE monolithic CMOS integrated circuit. Full Mil-Temp Electrical Performance from -55C to +125C The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The Controlled Baseline with One Wafer Fabrication Site and One Assembly/Test Site position of the wipers are controlled by the user through the 2 I C bus interface. Each potentiometer has an associated Full Homogeneous Lot Processing in Wafer Fab volatile Wiper Register (WR) and a non-volatile Initial Value No Combination of Wafer Fabrication Lots in Assembly Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the Full Traceability Through Assembly and Test by wiper. At power-up, the device recalls the contents of the two Date/Trace Code Assignment DCPs IVR to the corresponding WRs. Enhanced Process Change Notification The DCPs can be used as a three-terminal potentiometers Enhanced Obsolescence Management or as a two-terminal variable resistors in a wide variety of Eliminates Need for Up-Screening a COTS Component applications including control, parameter adjustments and signal processing. Four Potentiometers in One Package 128 Resistor Taps Device Information 2 I C Serial Interface The specifications for an Enhanced Product (EP) device are defined in a Vendor Item Drawing (VID), which is controlled - Three Address Pins, Up To Eight Devices/Bus by the Defense Logistics Agency (DLA). Hot-links to the Non-volatile Storage of Wiper Position applicable VID and other supporting application information Wiper Resistance: 70 Typical 3.3V are provided on our website. Shutdown Mode Pinout Shutdown Current 5A Max ISL22346WMVEP (20 LD TSSOP) Power Supply: 2.7V to 5.5V TOP VIEW 10k Total Resistance RH3 1 20 RW0 High Reliability RL3 2 19 RL0 - Endurance: 1,000,000 Data Changes Per Bit Per RW3 3 18 RH0 Register A2 4 17 SHDN - Register Data Retention: SCL 5 16 VCC - 10 years T +125C SDA 6 15 A1 - 15 years T +90C GND 7 14 A0 - 50 years T +55C RW2 8 13 RH1 20 Ld TSSOP RL2 9 12 RL1 RH2 10 11 RW1 Ordering Information VENDOR PART NUMBER RESISTANCE OPTION TEMP. PKG. (Notes 1, 2) VENDOR ITEM DRAWING PART MARKING (k ) RANGE (C) PACKAGE DWG. ISL22346WMVEP V62/08605-01XE 22346 WMVEP 10 -55 to +125 20 Ld TSSOP M20.173 NOTES: 1. Add -TK suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Devices must be procured to the VENDOR PART NUMBER. FN6624 Rev 1.00 Page 1 of 3 November 11, 2011ISL22346WM Block Diagram V CC RH3 WR3 SCL RW3 SDA POWER-UP RL3 2 INTERFACE, I C RH2 A0 CONTROL INTERFACE AND STATUS WR2 RW2 A1 LOGIC RL2 A2 RH1 WR1 RW1 RL1 NON- RH0 VOLATILE SHDN REGISTERS WR0 RW0 RL0 GND Pin Descriptions TSSOP PIN SYMBOL DESCRIPTION 1 RH3 High terminal of DCP3 2 RL3 Low terminal of DCP3 3 RW3 Wiper terminal of DCP3 2 4 A2 Device address input for the I C interface 2 5 SCL Open drain I C interface clock input 2 6 SDA Open drain Serial data I/O for the I C interface 7 GND Device ground pin 8 RW2 Wiper terminal of DCP2 9 RL2 Low terminal of DCP2 10 RH2 High terminal of DCP2 11 RW1 Wiper terminal of DCP1 12 RL1 Low terminal of DCP1 13 RH1 High terminal of DCP1 2 14 A0 Device address input for the I C interface 2 15 A1 Device address input for the I C interface 16 VCC Power supply pin 17 SHDN Shutdown active low input 18 RH0 High terminal of DCP0 19 RL0 Low terminal of DCP0 20 RW0 Wiper terminal of DCP0 FN6624 Rev 1.00 Page 2 of 3 November 11, 2011