X9521 Dual DCP, EEPROM Memory Data Sheet September 21, 2010 FN8207.2 DESCRIPTION Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules The X9521 combines two Digitally Controlled Potentiom- eters (DCPs), and integrated EEPROM with Block FEATURES TM Lock protection. All functions of the X9521 are accessed by an industry standard 2-Wire serial interface. Two Digitally Controlled Potentiometers (DCPs) 100 Tap - 10k The DCPs of the X9521 may be utilized to control the 256 Tap - 100k bias and modulation currents of the laser diode in a Fiber Non-Volatile Optic module. The 2kbit integrated EEPROM may be Write Protect Function used to store module definition data. 2kbit EEPROM Memory with Write Protect & Block TM Lock The features of the X9521 are ideally suited to simplifying 2-Wire industry standard Serial Interface the design of fiber optic modules which comply to the Gi- Complies to the Gigabit Interface Converter gabit Interface Converter (GBIC) specification. The inte- (GBIC) specification gration of these functions into one package significantly Single Supply Operation reduces board area, cost and increases reliability of laser 2.7V to 5.5V diode modules. Hot Pluggable 20 Ld TSSOP BLOCK DIAGRAM R H1 WIPER COUNTER R W1 REGISTER R L1 8 7 - BIT NONVOLATILE WP MEMORY PROTECT LOGIC R H2 CONSTAT WIPER COUNTER R W2 REGISTER DATA REGISTER 4 REGISTER R L2 SDA 8 - BIT COMMAND NONVOLATILE DECODE & MEMORY 2kbit CONTROL SCL EEPROM LOGIC ARRAY THRESHOLD RESET LOGIC CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. 2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. NOT RECOMMENDED FOR NEW DESIGNS POSSIBLE SUBSTITUTE PRODUCT X95820, ISL22326, ISL22329, ISL22323X9521 Ordering Information PRESET (FACTORY SHIPPED) V TRIPx PART NUMBER PART MARKING THRESHOLD LEVELS (x = 2, 3) TEMP RANGE (C) PACKAGE X9521V20I-A X9521VIA Optimized for 3.3V system monitoring -40 to +85 20 Ld TSSOP X9521V20I-B X9521VIB Optimized for 5V system monitoring -40 to +85 20 Ld TSSOP X9521V20IZ-A (Note) X9521VZIA Optimized for 3.3V system monitoring -40 to +85 20 Ld TSSOP (Pb-free) X9521V20IZ-B (Note) X9521VZIB Optimized for 5V system monitoring -40 to +85 20 Ld TSSOP (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PIN CONFIGURATION 20 Pin TSSOP Vcc R 1 20 H2 NC R W2 2 19 3 R 18 NC L2 NC 4 17 NC NC 5 NC 16 NC 6 NC 15 WP 7 14 NC SCL 8 13 R H1 SDA 9 12 R W1 V 11 R SS 10 L1 PIN ASSIGNMENT Pin Name Function R 1 Connection to end of resistor array for (the 256 Tap) DCP 2. H2 R 2 Connection to terminal equivalent to the Wiper of a mechanical potentiometer for DCP 2. w2 R 3 Connection to other end of resistor array for (the 256 Tap) DCP2. L2 Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile write operations. Also, when the Write Pro- tection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT 0,0 ), then 7WP no write (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal pull- down resistor, thus if left floating the write protection feature is disabled. Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input 8SCL and output. Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the de- 9SDA vice. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 10 Vss Ground. R 11 Connection to other end of resistor for (the 100 Tap) DCP 1. L1 R 12 Connection to terminal equivalent to the Wiper of a mechanical potentiometer for DCP 1 w1 R 13 Connection to end of resistor array for (the 100 Tap) DCP 1. H1 20 Vcc Supply Voltage. 4, 5, 6, 14, 15, NC No connect. 16, 17, 18, 19 FN8207.2 2 September 21, 2010