Datasheet 4.5V to 18V, 3A 1ch Synchronous Buck Converter BD86123AEFJ Description Features Input voltage range: 4.5V to 18.0V The BD86123AEFJ is synchronous buck converters. The Reference voltage 0.8V 1% device integrates power MOSFETS that provide a each Average output Current: 3A(Max.) maximums current output current continuous load current Switching frequency: 550kHz(Typ.) over a wide operating input voltage of 4.5V to 18V. Pch FET ON resistance: 90m(Typ.) Current mode operation provides fast transient response Nch FET ON resistance: 50m(Typ.) Standby current: 1 A (Typ.) and easy phase compensation. Operating temperature range: -40 to +85 The output power MOSFETs using P-type MOSEFT (HI Cycle by cycle over current protection(OCP) side) and N-type MOSEFT (LOW side), then this device Thermal shutdown (TSD) dont need boot capacitor. Under voltage lock out(UVLO) The BD86123AEFJ is HTSOP-J8 standard packages. Short circuit protection(SCP) Over voltage protection(OVP) Fixed soft start 5msec Applications Package W(Typ.) x D(Typ.) x H(Max.) LCD TVs HTSOP-J8 4.90mm x 6.00mm x 1.00mm Set top boxes DVD/Blu-ray players/recorders Broadband Network and Communication Interface (TOP VIEW) Amusement, other 1 8 SW PGND VIN 2 7 SW 3 6 COMP EN AGND 4 5 FB Figure 2. Pin configuration Typical Application BD86123AEFJ VIN L C1 SW PGND C2 R2 FB EN R3 COMP AGND R1 C3 Figure 1. Application Circuit Product structureSilicon monolithic integrated circuit This product is not designed protection against radioactive rays. www.rohm.com TSZ02201-0J2J0D100280-1-2 2012 ROHM Co., Ltd. All rights reserved. 1/20 TSZ2211114001 04.Sep.2012 Rev.001DatasheetDatasheet BD86123AEFJ Block Diagram EN VREG OSC OVP SCP OCP UVLO VIN IBIAS TSD S LOGIC ERR SW FB SLOP E PWM R COMP PGND SoftStart AGN D Figure 3. Block diagram Pin Description No. Symbol Description 1 PGND Power Ground pin. Power ground return for switching circuit. 2 VIN Input voltage supply pin. 3 EN Enable input control. Active high. 4 AGND Analog Ground pin. Electrically needs to be connected to PGND. 5 FB Converter feedback input. Connect to output voltage with feedback resistor divider. Error amplifier output, and input to the output switch current comparator. 6 COMP External loop compensation pin. 7 SW Switch node connection between high-side Pch FET and Low-side Nch FET. 8 SW Switch node connection between high-side Pch FET and Low-side Nch FET. Thermal Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected Back side Pad to AGND. www.rohm.com TSZ02201-0J2J0D100280-1-2 2012 ROHM Co., Ltd. All rights reserved. 2/20 TSZ2211115001 04.Sep.2012 Rev.001