Si500S SINGLE-ENDED OUTPUT SILICON OSCILLATOR Features Quartz-free, MEMS-free, and PLL-free all-silicon oscillator Footprint compatible with industry- standard 3.2 x 5.0 mm XOs Any output frequencies from 0.9 to 200 MHz CMOS and SSTL versions available Short lead times Driver stopped, tri-state, or powerdown Excellent temperature stability (20 ppm) operation Highly reliable startup and operation RoHS compliant High immunity to shock and vibration 1.8, 2.5, or 3.3 V options Low jitter: <1.5 ps rms Low power 0 to 85 C operation includes 10-year aging in hot More than 10x better fit rate than environments competing crystal solutions Specifications Parameters Condition Min Typ Max Units Frequency Range 0.9 200 MHz Temperature stability, 10 ppm 0 to +70 C Temperature stability, 20 ppm 0 to +85 C Frequency Stability Total stability, 150 ppm 1 0 to +70 C operation Total stability, 250 ppm 2 0 to +85 C operation Commercial 0 70 C Operating Temperature Extended commercial 0 85 C Storage Temperature 55 +125 C 1.8 V option 1.71 1.98 V Supply Voltage 2.5 V option 2.25 2.75 V 3.3 V option 2.97 3.63 V Notes: 1. Inclusive of 25 C initial frequency accuracy, operating temperature range, supply voltage change, output load change, first-year aging at 25 C, shock, vibration, and one solder reflow. 2. Inclusive of 25 C initial frequency accuracy, operating temperature range, supply voltage change, output load change, ten-year aging at 85 C, shock, vibration, and one solder reflow. 3. See AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators for further details regarding output clock termination recommendations. 4. V = .5 x V . TT DD 5. V = .45 x V . TT DD Rev. 1.1 10/11 Copyright 2011 by Silicon Laboratories Si500SSi500S Parameters Condition Min Typ Max Units 1.8 V option, 40 pF, 40 MHz, CMOS 13.9 16 mA 1.8 V option, 10 pF, 200 MHz, CMOS 16.7 19 mA 2.5 V option, 40 pF, 40 MHz, CMOS 15.8 18 mA 2.5 V option, 10 pF, 200 MHz, CMOS 19.3 22 mA 3.3 V option, 40 pF, 40 MHz, CMOS 17.7 20 mA 3.3 V option, 10 pF, 200 MHz, CMOS 21.5 24 mA Supply Current SSTL-3.3, 200 MHz 18.1 20.2 mA SSTL-2.5, 200 MHz 18.0 19.7 mA SSTL-1.8, 200 MHz 16.8 18.7 mA Output Stopped, CMOS 11.8 13.1 mA Tri-State 9.7 10.7 mA Powerdown 1.0 1.9 mA 54 + Output Symmetry 0.5 x V 46 13 ns/T % DD CLK 13 ns/T CLK CMOS, C = 15 pF measured from L 1.4 2.0 ns 3 20 to 80% of V Rise and Fall Times DD SSTL 0.6 ns V , sourcing 9 mA V 0.5 V OH DD CMOS Output Voltage V , sinking 9 mA 0.5 V OL V V + 0.375 OH TT 4 SSTL-1.8 Output Voltage V V 0.375 V OL TT V V + 0.48 OH TT 4 SSTL-2.5 Output Voltage V V V 0.48 OL TT V V + 0.48 OH TT 5 SSTL-3.3 Output Voltage V V V 0.48 OL TT crosses min spec From time V DD Powerup Time 2 ms supply 250 + OE Deassertion to Clk Stop ns 3xT CLK Return from Output Driver 250 + ns Stopped Mode 3xT CLK Return from Tri-State Time 12 + 3 x T s CLK Return from Powerdown Time 2 ms ps 3 Period Jitter (1-sigma) SSTL 1 2 RMS 1MHz0.4 xF , SSTL or CMOS OUT ps Integrated Phase Jitter and C < 7pF, 0.7 1.5 L RMS F > 2.5 MHz OUT Notes: 1. Inclusive of 25 C initial frequency accuracy, operating temperature range, supply voltage change, output load change, first-year aging at 25 C, shock, vibration, and one solder reflow. 2. Inclusive of 25 C initial frequency accuracy, operating temperature range, supply voltage change, output load change, ten-year aging at 85 C, shock, vibration, and one solder reflow. 3. See AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators for further details regarding output clock termination recommendations. 4. V = .5 x V . TT DD 5. V = .45 x V . TT DD 2 Rev. 1.1