M24256-DRMN8TPK

M24256-DRE 256-Kbit serial IC bus EEPROM - 105C operation Datasheet - production data Features 2 Compatible with all I C bus modes 1 MHz 400 kHz 100 kHz Memory array TSSOP8 (DW) 256 Kbits (32 Kbytes) of EEPROM 169 mil width Page size: 64 bytes Additional Write lockable page (Identification page) Extended temperature and voltage range -40 C to 105 C 1.7 V to 5.5 V Schmitt trigger inputs for noise filtering Short Write cycle time SO8 (MN) Byte Write within 4 ms 150 mil width Page Write within 4 ms Write cycle endurance 4 million Write cycles at 25 C 1.2 million Write cycles at 85 C 900 k Write cycles at 105 C WFDFPN8 (MF) Data retention DFN8 - 2 x 3 mm more than 50 years at 105 C 200 years at 55 C ESD Protection (Human Body Model) 4000 V Packages RoHS compliant and halogen-free (ECOPACK2 ) January 2017 DocID027418 Rev 2 1/42 This is information on a product in full production. www.st.comContents M24256-DRE Contents 1 Description . 6 2 Signal description . 8 2.1 Serial Clock (SCL) . 8 2.2 Serial Data (SDA) 8 2.3 Chip Enable (E2, E1, E0) 8 2.4 Write Control (WC) . 8 2.5 V (ground) . 9 SS 2.6 Supply voltage (V ) . 9 CC 3 Device operation . 10 3.1 Start condition .11 3.2 Stop condition .11 3.3 Data input 11 3.4 Acknowledge bit (ACK) .11 3.5 Device addressing 12 3.6 Identification page 14 4 Instructions . 15 4.1 Write operations 15 4.1.1 Byte Write . 16 4.1.2 Page Write . 17 4.1.3 Write Identification Page 18 4.1.4 Lock Identification Page . 18 4.1.5 Minimizing Write delays by polling on ACK 19 4.2 Read operations 20 4.2.1 Random Address Read . 20 4.2.2 Current Address Read 21 4.2.3 Sequential Read 21 4.2.4 Read Identification Page 21 4.2.5 Read the lock status . 21 4.2.6 Acknowledge in Read mode . 22 2/42 DocID027418 Rev 2