M48Z512A M48Z512AY, M48Z512AV 4 Mbit (512 Kbit x 8) ZEROPOWER SRAM Not recommended for new design Features Integrated, ultra low power SRAM, power-fail control circuit, and battery Conventional SRAM operation unlimited WRITE cycles 32 1 10 years of data retention in the absence of power Automatic power-fail chip deselect and WRITE PMDIP32 module protection Two WRITE protect voltages: (V = power-fail deselect voltage) PFD Description M48Z512A: V = 4.75 to 5.5 V CC 4.5 V V 4.75 V PFD The M48Z512A/Y/V ZEROPOWER RAM is a M48Z512AY: V = 4.5 to 5.5 V non-volatile, 4,194,304-bit static RAM organized CC 4.2 V V 4.5 V as 524,288 words by 8 bits. The devices combine PFD an internal lithium battery, a CMOS SRAM and a M48Z512AV: V = 3.0 to 3.6 V CC control circuit in a plastic, 32-pin DIP module. 2.8 V V 3.0 V PFD Battery internally isolated until power is applied Pin and function compatible with JEDEC standard 512 K x 8 SRAMs PMDIP32 is an ECOPACK package RoHS compliant Lead-free second level interconnect June 2011 Doc ID 5146 Rev 9 1/21 This is information on a product still in production but not recommended for new designs. www.st.com 1Contents M48Z512A, M48Z512AY, M48Z512AV Contents 1 Device overview 5 2 Operating modes 7 2.1 READ mode 7 2.2 WRITE mode . 9 2.3 Data retention mode . 11 2.4 V noise and negative going transients . 12 CC 3 Maximum ratings . 13 4 DC and AC parameters 14 5 Package mechanical data 17 6 Part numbering 18 7 Environmental information . 19 8 Revision history . 20 2/21 Doc ID 5146 Rev 9