TC74HCT245AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT245AP,TC74HCT245AF Octal Bus Transceiver (3-state) The TC74HCT245A is high speed CMOS OCTAL BUS 2 TC74HCT245AP TRANSCEIVER fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Its inputs are compatible with TTL, NMOS, and CMOS output voltage levels. It is intended for two-way asynchronous communication between data busses. The direction of data transmission is determined by the level of the DIR input. The enable input ( G ) can be used to disable the device so that the busses are effectively isolated. TC74HCT245AF All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features (Note 1) (Note 2) High speed: t = 10 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 4 A (max) at Ta = 25C CC Compatible with TTL outputs: V = 0.8 V (max) IL V = 2.0 V (min) IH Weight Wide interfacing ability: LSTTL, NMOS, CMOS DIP20-P-300-2.54A : 1.30 g (typ.) Output drive capability: 15 LSTTL loads SOP20-P-300-1.27A : 0.22 g (typ.) Symmetrical output impedance: I = I = 6 mA (min) OH OL Balanced propagation delays: t t pLH pHL Pin and function compatible with 74LS245 Note 1: Do not apply a signal to any bus terminal when it is the output mode. Damage may result. Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or down resistors. Pin Assignment 1 2007-10-01 TC74HCT245AP/AF IEC Logic Symbol Truth Table Inputs Function Output G DIR A Bus B Bus L L Output Input A = B L H Input Output B = A H X Z Z X: H or L Z: High impedance Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range V 0.5 to 7 V CC DC input voltage V 0.5 to V + 0.5 V IN CC DC output voltage V 0.5 to V + 0.5 V OUT CC Input diode current I 20 mA IK Output diode current I 20 mA OK DC output current I 35 mA OUT DC V /ground current I 75 mA CC CC Power dissipation P 500 (DIP) (Note 2)/180 (SOP) mW D Storage temperature T 65 to 150 C stg Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = 40 to 65C. From Ta = 65 to 85C a derating factor of 10 mW/C shall be applied until 300 mW. 2 2007-10-01