INTERLACER Video Interlacer Rev. 1.1 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, reset ASIC and SoC Supplied as human readable VHDL (or Verilog) source code Video interlacer converts any progressive video format to its LINE PIXEL interlaced equivalent e.g. 1080p to 1080i COUNTER COUNTER RGB or YCbCr RGB or YCbCr Supports 24-bit RGB or 4:4:4 YCbCr pixels pixin pixout 24 24 16 16 Supports all video resolutions up to 2 x 2 pixout field Fully pipelined architecture with simple valid-ready flow control FLOW pixin vsync pixout vsync CONTROL Self-flushing design operates like a simple FIFO AND pixin hsync pixout hsync MULTIPLEXING One frame in generates one interlaced field out pixin val pixout val Output rate is one pixel per clock pixin rdy pixout rdy Supports 300 MHz+ operation on basic FPGA devices clk Applications 16 16 Conversion of all standard and custom video formats such as 1920x1080p to 1920x1080i, 720x480p to 720x480i etc. Video solutions for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc. Figure 1: Video interlacer architecture Pin-out Description General Description Pin name I/O Description Active state clk in Synchronous clock rising edge The INTERLACER IP Core (Figure 1) is a fully pipelined video interlacer solution that converts any progressive video format into its interlaced reset in Asynchronous reset low equivalent. The format of the input video is defined by the parameters pixels per line in Number of pixels per input data pixels per line and lines per frame. These values specify the size of 15:0 line of video one input frame of video in pixels and lines. Each interlaced output field will have half the number of lines as an input frame. lines per frame in Number of lines per input data 15:0 frame of video The input and output interfaces are streaming interfaces that follow a 1 pixin 23:0 in 24-bit input pixel data simple valid-ready pipeline protocol . Input pixels and syncs are sampled on the rising edge of clk when pixin val and pixin rdy are both high. pixin vsync in Vertical sync in high Likewise, output pixels and syncs are sampled on the rising edge of clk when pixout val and pixout rdy are high. The interfaces are compatible pixin hsync in Horizontal sync in high with all Zipcores video IP Cores and allow for easy connectivity between pixin val in Input pixel valid high modules. pixin rdy out Ready to accept input high The input sync signals vsync and hsync are sideband flags that are pixel (handshake signal) coincident with the first pixel of a frame and the first pixel of a line pixout 23:0 out 24-bit output pixel data respectively. The output sync signals are coincident with the first pixel of an output field. Note that the output interface has an additional field flag pixout field out Output field number 0: odd, 1: even that identifies whether the field is odd or even. This field flag is held high or low for the duration of the output field. pixout vsync out Vertical sync out high pixout hsync out Horizontal sync out high Note that if no flow control is required in the design and the output is guaranteed to accept pixels without stalling, then the signal pixout rdy pixout val out Output pixel valid high may be tied high and the signal pixin rdy may be ignored. pixout rdy in Ready to accept output high pixel (handshake signal) 1 Please see Zipcores application note: app note zc001.pdf for more examples of how to use the valid-ready pipeline protocol Copyright 2019 www.zipcores.com Download this IP Core Page 1 of 3 pixels per line lines per frameINTERLACER Video Interlacer Rev. 1.1 Functional Timing Pixel invalid - ignore clk Figure 2 shows the signalling at the input to the interlacer at the start of a new frame. The first line of a new frame begins with pixin vsync and pixout Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 pixin hsync asserted high together with the first pixel. Note that the pixout field signals pixin, pixin vsync and pixin hsync are only valid if pixin val is also asserted high. pixout vsync In addition, the diagram shows what happens when pixin rdy is de- pixout hsync asserted. In this case, the pipeline is stalled and the upstream interface must hold-off before further pixels are processed. pixout val pixout rdy Pipeline stall Start of new output field clk pixin Figure 4: First pixel of a new output field also showing invalid output Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 pixel for one clock cycle pixin vsync pixin hsync Source File Description pixin val pixin rdy All source files are provided as text files coded in VHDL. The following table gives a brief description of each file. Start of new frame Source file Description Figure 2: First pixel of an new input frame (and line) also showing an video in.txt Text-based source video file example of a pipeline stall for one clock cycle video file reader.vhd Reads text-based source video file interlacer.vhd Interlacer top-level component Figure 3 shows the signalling at the beginning of a new line only. The first pixel of a new line is specified with pixin vsync asserted low and interlacer bench.vhd Top-level test bench pixin hsync asserted high. This time, there is no pipeline stalling shown. Functional Testing clk pixin An example VHDL testbench is provided for use in a suitable VHDL Pixel 0 Pixel 1 Pixel 2 Pixel 2 Pixel 4 Pixel 5 simulator. The compilation order of the source code is as follows: pixin vsync pixin hsync 1. video file reader.vhd 2. interlacer.vhd pixin val 3. interlacer bench.vhd pixin rdy The VHDL testbench instantiates the INTERLACER component with the Start of new line parameters set up for a 720 x 480 source image. The source video for the simulation is generated by the video file-reader Figure 3: First pixel of a new input line component. This component reads a text-based file which contains the RGB pixel data. The text file is called video in.txt and should be placed in the top-level simulation directory. Finally, figure 4 shows the signalling at the output of the interlacer. The output uses exactly the same protocol as the input with the exception of The file video in.txt follows a simple format which defines the state of the additional pixout field flag. The pixout field flag indicates whether the signals: pixin val, pixin vsync, pixin hsync and pixin on a clock-by-clock output field is odd or even. basis. An example file might be the following: In this particular example, it shows pixout val de-asserted for 1 clock- cycle, in which case, the output pixel should be ignored. Remember that 1 1 1 00 11 22 pixel 0 line 0 (start of frame) transfers at the interface are only permitted when valid and ready are both 1 0 0 33 44 55 pixel 1 simultaneously high. 0 0 0 00 00 00 don t care 1 0 0 66 77 88 pixel 2 1 0 1 00 11 22 pixel 0 line 1 etc.. Copyright 2019 www.zipcores.com Download this IP Core Page 2 of 3