N74F280BN,602

INTEGRATED CIRCUITS 74F280B 9-bit odd/even parity generator/checker Product specification 1996 Mar 12 IC15 Data Handbook Philips Semiconductors Product specification 9-bit odd/even parity generator/checker 74F280B FEATURES PIN CONFIGURATION High-impedance NPN base inputs for reduced loading (20A in Low and High states) 1 14 I V 6 CC Buffered inputs one normalized load I 2 13 I 7 5 NC 3 12 I Word length easily expanded by cascading 4 I 4 11 I 8 3 Industrial temperature range available (40C to +85C) E 5 10 I 2 6 9 I O 1 DESCRIPTION The 74F280B is a 9-bit Parity Generator or Checker commonly used GND 7 8 I 0 to detect errors in high speed data transmission or data retrieval systems. Both Even ( ) and Odd ( ) parity outputs are available E O SF00849 for generating or checking even or odd parity on up to 9 bits. The Even ( ) parity output is High when an even number of Data E inputs (I - I ) are High. The Odd ( ) parity output is High when an 0 8 O TYPICAL TYPICAL odd number of Data inputs are High. PROPAGATION SUPPLY CURRENT TYPE Expansion to larger word sizes is accomplished by tying the Even DELAY (TOTAL) ( ) outputs of up to nine parallel devices to the data inputs of the E 74F280B 5.5ns 26mA final stage. This expansion scheme allows an 81-bit data word to be checked in less than 20ns. ORDERING INFORMATION COMMERCIAL RANGE INDUSTRIAL RANGE DESCRIPTION V = 5V 10%, V = 5V 10%, PKG. DWG. CC CC T = 0C to +70C T = 40C to +85C amb amb 14-pin plastic DIP N74F280BN I74F280BN SOT27-1 14-pin plastic SO N74F280BD I74F280BD SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 74F(U.L.) LOAD VALUE PINS DESCRIPTION HIGH/LOW HIGH/LOW I - I Data inputs 1.0/0.033 20A/20A 0 8 , Parity outputs 50/33 1.0mA/20mA E O NOTE: One (1.0) FAST Unit Load is defined as: 20A in the High state and 0.6mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 8 9 10 11 12 13 1 2 4 8 2K 9 10 I I I I I I I I I 0 1 2 3 4 5 6 7 8 11 5 E 12 13 E O 6 1 O 2 56 4 V =Pin 14 CC GND=Pin 7 SF00845 SF00846 2 1996 Mar 12 853-0363 16555