4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA Data Sheet AD7193 FEATURES Pressure measurement Temperature measurement Fast settling filter option Flow measurement 4 differential/8 pseudo differential input channels Weigh scales RMS noise: 11 nV 4.7 Hz (gain = 128) Chromatography 15.5 noise-free bits 2.4 kHz (gain = 128) Medical and scientific instrumentation Up to 22 noise-free bits (gain = 1) Offset drift: 5 nV/C GENERAL DESCRIPTION Gain drift: 1 ppm/C The AD7193 is a low noise, complete analog front end for high Specified drift over time precision measurement applications. It contains a low noise, Automatic channel sequencer 24-bit sigma-delta (-) analog-to-digital converter (ADC). Programmable gain (1 to 128) The on-chip low noise gain stage means that signals of small Output data rate: 4.7 Hz to 4.8 kHz amplitude can interface directly to the ADC. Internal or external clock The device can be configured to have four differential inputs or Simultaneous 50 Hz/60 Hz rejection eight pseudo differential inputs. The on-chip channel sequencer 4 general-purpose digital outputs allows several channels to be enabled simultaneously, and the Power supply AD7193 sequentially converts on each enabled channel, simplifying AV : 3 V to 5.25 V DD DV : 2.7 V to 5.25 V communication with the part. The on-chip 4.92 MHz clock can DD Current: 4.65 mA be used as the clock source to the ADC or, alternatively, an external Temperature range: 40C to +105C clock or crystal can be used. The output data rate from the part 28-lead TSSOP and 32-lead LFCSP packages can be varied from 4.7 Hz to 4.8 kHz. Interface The device has a very flexible digital filter, including a fast 3-wire serial settling option. Variables such as output data rate and settling SPI, QSPI, MICROWIRE, and DSP compatible time are dependent on the option selected. The AD7193 also Schmitt trigger on SCLK includes a zero latency option. APPLICATIONS The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.65 mA, and it is available in a 28-lead PLC/DCS analog input modules TSSOP package and a 32-lead LFCSP package. Data acquisition Strain gage transducers FUNCTIONAL BLOCK DIAGRAM AV AGND DV DGND REFIN1(+) REFIN1() DD DD AD7193 AIN1 AIN2 AIN3 DOUT/RDY AIN4 SERIAL AIN5 INTERFACE MUX DIN - PGA AND AIN6 ADC CONTROL SCLK AIN7 LOGIC AIN8 CS AINCOM SYNC TEMP P3 SENSOR P2 BPDSW CLOCK CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2() P1/REFIN2(+) Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com 08367-001AD7193 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Reference ..................................................................................... 32 Applications ....................................................................................... 1 Reference Detect ......................................................................... 33 General Description ......................................................................... 1 Bipolar/Unipolar Configuration .............................................. 33 Functional Block Diagram .............................................................. 1 Data Output Coding .................................................................. 33 Revision History ............................................................................... 3 Burnout Currents ....................................................................... 33 Specifications ..................................................................................... 4 Channel Sequencer .................................................................... 33 Timing Characteristics ................................................................ 8 Digital Interface .......................................................................... 34 Absolute Maximum Ratings .......................................................... 10 Reset ............................................................................................. 38 Thermal Resistance .................................................................... 10 System Synchronization ............................................................ 38 ESD Caution ................................................................................ 10 Enable Parity ............................................................................... 38 Pin Configurations and Function Descriptions ......................... 11 Clock ............................................................................................ 38 Typical Performance Characteristics ........................................... 15 Bridge Power-Down Switch ...................................................... 38 RMS Noise and Resolution............................................................ 18 Temperature Sensor ................................................................... 39 4 Sinc Chop Disabled ................................................................... 18 Logic Outputs ............................................................................. 39 3 Sinc Chop Disabled ................................................................... 19 Calibration................................................................................... 39 Fast Settling ................................................................................. 20 Digital Filter .................................................................................... 41 4 On-Chip Registers .......................................................................... 21 Sinc Filter (Chop Disabled) ..................................................... 41 3 Communications Register ......................................................... 22 Sinc Filter (Chop Disabled) ..................................................... 43 4 Status Register ............................................................................. 23 Chop Enabled (Sinc Filter) ...................................................... 45 3 Mode Register ............................................................................. 24 Chop Enabled (Sinc Filter) ...................................................... 47 4 Configuration Register .............................................................. 27 Fast Settling Mode (Sinc Filter) ............................................... 48 3 Data Register ............................................................................... 29 Fast Settling Mode (Sinc Filter) ............................................... 50 ID Register ................................................................................... 29 Fast Settling Mode (Chop Enabled) ......................................... 51 GPOCON Register ..................................................................... 29 Summary of Filter Options ....................................................... 52 Offset Register ............................................................................. 30 Grounding and Layout .................................................................. 53 Full-Scale Register ...................................................................... 30 Applications Information .............................................................. 54 ADC Circuit Information .............................................................. 31 Flowmeter .................................................................................... 54 Overview ...................................................................................... 31 Outline Dimensions ....................................................................... 55 Analog Input Channel ............................................................... 32 Ordering Guide .......................................................................... 55 Programmable Gain Array (PGA) ........................................... 32 Rev. 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