Dual Channel, 20 MHz 10-Bit a Resolution CMOS ADC AD9201 FUNCTIONAL BLOCK DIAGRAM FEATURES Complete Dual Matching ADCs AVDD AVSS DVDD DVSS CLOCK Low Power Dissipation: 215 mW (+3 V Supply) Single Supply: 2.7 V to 5.5 V IINA I AD9201 SLEEP ADC REGISTER Differential Nonlinearity Error: 0.4 LSB IINB SELECT On-Chip Analog Input Buffers REFERENCE IREFB BUFFER On-Chip Reference IREFT THREE- Signal-to-Noise Ratio: 57.8 dB QREFB ASYNCHRONOUS STATE DATA QREFT MULTIPLEXER OUTPUT 10 BITS Over Nine Effective Bits BUFFER VREF Spurious-Free Dynamic Range: 73 dB 1V REFSENSE No Missing Codes Guaranteed CHIP SELECT 28-Lead SSOP QINB Q ADC REGISTER QINA PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9201 is a complete dual channel, 20 MSPS, 10-bit 1. Dual 10-Bit, 20 MSPS ADCs CMOS ADC. The AD9201 is optimized specifically for applica- A pair of high performance 20 MSPS ADCs that are opti- tions where close matching between two ADCs is required (e.g., mized for spurious free dynamic performance are provided for I/Q channels in communications applications). The 20 MHz encoding of I and Q or diversity channel information. sampling rate and wide input bandwidth will cover both narrow- 2. Low Power band and spread-spectrum channels. The AD9201 integrates two Complete CMOS Dual ADC function consumes a low 10-bit, 20 MSPS ADCs, two input buffer amplifiers, an internal 215 mW on a single supply (on 3 V supply). The AD9201 voltage reference and multiplexed digital output buffers. operates on supply voltages from 2.7 V to 5.5 V. Each ADC incorporates a simultaneous sampling sample-and- 3. On-Chip Voltage Reference hold amplifier at its input. The analog inputs are buffered no The AD9201 includes an on-chip compensated bandgap external input buffer op amp will be required in most applica- voltage reference pin programmable for 1 V or 2 V. tions. The ADCs are implemented using a multistage pipeline 4. On-chip analog input buffers eliminate the need for external architecture that offers accurate performance and guarantees no op amps in most applications. missing codes. The outputs of the ADCs are ported to a multi- plexed digital output buffer. 5. Single 10-Bit Digital Output Bus The AD9201 ADC outputs are interleaved onto a single The AD9201 is manufactured on an advanced low cost CMOS output bus saving board space and digital pin count. process, operates from a single supply from 2.7 V to 5.5 V, and consumes 215 mW of power (on 3 V supply). The AD9201 input 6. Small Package structure accepts either single-ended or differential signals, The AD9201 offers the complete integrated function in a providing excellent dynamic performance up to and beyond compact 28-lead SSOP package. its 10 MHz Nyquist input frequencies. 7. Product Family The AD9201 dual ADC is pin compatible with a dual 8-bit ADC (AD9281) and has a companion dual DAC product, the AD9761 dual DAC. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: (AVDD = +3 V, DVDD = +3 V, F = 20 MSPS, VREF = 2 V, INB = 0.5 V, T to T SAMPLE MIN MAX, AD9201SPECIFICATIONS internal ref, differential input signal, unless otherwise noted) Parameter Symbol Min Typ Max Units Condition RESOLUTION 10 Bits CONVERSION RATE F 20 MHz S DC ACCURACY Differential Nonlinearity DNL 0.4 LSB REFT = 1 V, REFB = 0 V Integral Nonlinearity INL 1.2 LSB Differential Nonlinearity (SE) DNL 0.5 1 LSB REFT = 1 V, REFB = 0 V Integral Nonlinearity (SE) INL 1.5 2.5 LSB Zero-Scale Error, Offset Error E 1.5 3.8 % FS ZS 3.5 5.4 % FS Full-Scale Error, Gain Error E FS Gain Match 0.5 LSB Offset Match 5 LSB ANALOG INPUT Input Voltage Range AIN 0.5 AVDD/2 V Input Capacitance C 2pF IN Aperture Delay t 4ns AP Aperture Uncertainty (Jitter) t 2ps AJ Aperture Delay Match 2 ps Input Bandwidth (3 dB) BW Small Signal (20 dB) 240 MHz Full Power (0 dB) 245 MHz INTERNAL REFERENCE Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF Output Voltage Tolerance (1 V Mode) 10 mV Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND Output Voltage Tolerance (2 V Mode) 15 mV Load Regulation (1 V Mode) 28 mV 1 mA Load Current Load Regulation (2 V Mode) 15 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 2.7 3 5.5 V AVDD DVDD 2.3 V DRVDD 2.7 3 5.5 V 71.6 mA AVDD = 3 V Supply Current I AVDD 0.1 mA I DRVDD 215 245 mW AVDD = DVDD = 3 V Power Consumption P D Power-Down 15.5 mW STBY = AVDD, Clock = AVSS Power Supply Rejection PSR 0.8 1.3 % FS 1 DYNAMIC PERFORMANCE Signal-to-Noise and Distortion SINAD f = 3.58 MHz 55.6 57.3 dB f = 10 MHz 55.8 dB Signal-to-Noise SNR f = 3.58 MHz 55.9 57.8 dB f = 10 MHz 56.2 dB Total Harmonic Distortion THD f = 3.58 MHz 69 63.3 dB f = 10 MHz 66.3 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz 66 73 dB f = 10 MHz 70.5 dB 2 Two-Tone Intermodulation Distortion IMD 62 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.1 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.05 % F = 14.3 MHz S Crosstalk Rejection 68 dB REV. D 2