Dual Channel 8-Bit a Resolution CMOS ADC AD9281 FUNCTIONAL BLOCK DIAGRAM FEATURES Complete Dual Matching ADC AVDD AVSS CLOCK DVDD DVSS Low Power Dissipation: 225 mW (+3 V Supply) Single Supply: 2.7 V to 5.5 V IINA I SLEEP Differential Nonlinearity Error: 0.1 LSB ADC AD9281 REGISTER IINB On-Chip Analog Input Buffers SELECT REFERENCE IREFB On-Chip Reference BUFFER IREFT Signal-to-Noise Ratio: 49.2 dB THREE- QREFB ASYNCHRONOUS STATE DATA Over Seven Effective Bits QREFT MULTIPLEXER OUTPUT 8 BITS Spurious-Free Dynamic Range: 65 dB BUFFER VREF 1V No Missing Codes Guaranteed REFSENSE CHIP 28-Lead SSOP SELECT QINB Q ADC REGISTER QINA PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9281 is a complete dual channel, 28 MSPS, 8-bit 1. Dual 8-Bit, 28 MSPS ADC CMOS ADC. The AD9281 is optimized specifically for applica- A pair of high performance 28 MSPS ADCs that are opti- tions where close matching between two ADCs is required (e.g., mized for spurious free dynamic performance are provided for I/Q channels in communications applications). The 28 MHz encoding of I and Q or diversity channel information. sampling rate and wide input bandwidth will cover both narrow- 2. Low Power band and spread-spectrum channels. The AD9281 integrates Complete CMOS Dual ADC function consumes a low two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal 225 mW on a single supply (on 3 V supply). The AD9281 voltage reference and multiplexed digital output buffers. operates on supply voltages from 2.7 V to 5.5 V. Each ADC incorporates a simultaneous sampling sample-and- 3. On-Chip Voltage Reference hold amplifier at its input. The analog inputs are buffered no The AD9281 includes an on-chip compensated bandgap external input buffer op amp will be required in most applica- voltage reference pin programmable for 1 V or 2 V. tions. The ADCs are implemented using a multistage pipeline 4. On-chip analog input buffers eliminate the need for external architecture that offers accurate performance and guarantees no op amps in most applications. missing codes. The outputs of the ADCs are ported to a multi- plexed digital output buffer. 5. Single 8-Bit Digital Output Bus The AD9281 ADC outputs are interleaved onto a single The AD9281 is manufactured on an advanced low cost CMOS output bus saving board space and digital pin count. process, operates from a single supply from 2.7 V to 5.5 V, and consumes 225 mW of power (on 3 V supply). The AD9281 6. Small Package input structure accepts either single-ended or differential signals, The AD9281 offers the complete integrated function in a providing excellent dynamic performance up to and beyond compact 28-lead SSOP package. 14 MHz Nyquist input frequencies. 7. Product Family The AD9281 dual ADC is pin compatible with a dual 10-bit ADC (AD9201). REV. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: (AVDD = +3 V, DVDD = +3 V, F = 28 MSPS, VREF = 2 V, INB = 0.5 V, T to T SAMPLE MIN MAX AD9281SPECIFICATIONS unless otherwise noted) Parameter Symbol Min Typ Max Units Condition RESOLUTION 8 Bits CONVERSION RATE F 28 MHz (32 MHz at +25C) S DC ACCURACY Differential Nonlinearity DNL 0.1 LSB REFT = 1.0 V, REFB = 0.0 V Integral Nonlinearity INL 0.25 LSB 1 Differential Nonlinearity (SE) DNL 0.2 1.0 LSB REFT = 1.0 V, REFB = 0.0 V 1 Integral Nonlinearity (SE) INL 0.3 1.5 LSB Zero-Scale Error, Offset Error E 1 3.2 % FS ZS Full-Scale Error, Gain Error E 1.2 5.4 % FS FS Gain Match 0.2 LSB Offset Match 1.2 LSB ANALOG INPUT Input Voltage Range AIN 0.5 AVDD/2 V Input Capacitance C 2pF IN Aperture Delay t 4ns AP Aperture Uncertainty (Jitter) t 2ps AJ Aperture Delay Match 2 ps Input Bandwidth (3 dB) BW Small Signal (20 dB) 240 MHz Full Power (0 dB) 245 MHz INTERNAL REFERENCE Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF Output Voltage Tolerance (1 V Mode) 10 mV Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND Output Voltage Tolerance (2 V Mode) 15 mV Load Regulation (1 V Mode) VREF 10 35 mV 1 mA Load Current Load Regulation (2 V Mode) 15 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 2.7 3 5.5 V DVDD 2.7 3 5.5 V Supply Current I 75 mA AVDD I 0.1 mA DVDD Power Consumption P 225 260 mW D Power-Down 16 mW STBY = AVDD, Clock Low Power Supply Rejection PSR 0.15 0.75 % FS 2 DYNAMIC PERFORMANCE Signal-to-Noise and Distortion SINAD f = 3.58 MHz 46.4 49.1 dB f = 14 MHz 48 dB Signal-to-Noise SNR f = 3.58 MHz 47.8 49.2 dB f = 14 MHz 48.5 dB Total Harmonic Distortion THD f = 3.58 MHz 67.5 49.5 dB f = 14 MHz 60 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz 49.6 65 dB f = 14 MHz 56 dB 3 Two-Tone Intermodulation Distortion IMD 58 dB f = 44.9 MHz and 45.52 MHz Differential Phase DP 0.2 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.08 % F = 14.3 MHz S Crosstalk Rejection 62 dB REV. F 2