10-Bit, 210 MSPS ADC AD9410 FEATURES FUNCTIONAL BLOCK DIAGRAM REF REF V V V IN OUT AGND DGND D DD CC SNR = 54 dB with 99 MHz analog input 500 MHz analog bandwidth AD9410 On-chip reference and track and hold REFERENCE OR A 10 1.5 V p-p differential analog input range PORT D D A9 A0 A 5.0 V and 3.3 V supply operation A ADC 10 IN 3.3 V CMOS/TTL outputs T/H 10-BIT A IN CORE Power: 2.1 W typical at 210 MSPS OR B 10 PORT Demultiplexed outputs each at 105 MSPS D D B9 B0 B DS Output data format option DS TIMING AND CLK+ SYNCHRONIZATION Data sync input and data clock output provided CLK DCO Interleaved or parallel data output option DCO DFS I/P APPLICATIONS Figure 1. Communications and radars Local multipoint distribution services (LMDS) High-end imaging systems and projectors Cable reverse paths Point-to-point radio links GENERAL DESCRIPTION The AD9410 is a 10-bit monolithic sampling analog-to-digital Fabricated on an advanced BiCMOS process, the AD9410 is converter (ADC) with an on-chip track-and-hold circuit and is available in an 80-lead thin quad flat package, exposed pad optimized for high speed conversion and ease of use. The product specified over the industrial temperature range (40C to +85C). operates at a 210 MSPS conversion rate, with outstanding PRODUCT HIGHLIGHTS dynamic performance over its full operating range. 1. High Resolution at High SpeedThe architecture is spe- The ADC requires a 5.0 V and 3.3 V power supply and up to a cifically designed to support conversion up to 210 MSPS 210 MHz differential clock input for full performance operation. with outstanding dynamic performance. No external reference or driver components are required for many 2. Demultiplexed OutputOutput data is decimated by two applications. The digital outputs are TTL-/CMOS-compatible and and provided on two data ports for ease of data transport. separate output power supply pins also support interfacing with 3.3 V logic. 3. Output Data ClockThe AD9410 provides an output data clock synchronous with the output data, simplifying the The clock input is differential and TTL-/CMOS-compatible. timing between data and other logic. The 10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V) supplies. Two output buses support demultiplexed data 4. Data SynchronizationA DS input is provided to allow for up to 105 MSPS rates and binary or twos complement output synchronization of two or more AD9410s in a system, or to coding format is available. A data sync function is provided for synchronize data to a specific output port in a single timing-dependent applications. An output clock simplifies AD9410 system. interfacing to external logic. The output data bus timing is selectable for parallel or interleaved mode, allowing for flexibility in latching output data. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20002007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 01679-001AD9410 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................8 Applications....................................................................................... 1 Terminology.................................................................................... 10 Functional Block Diagram .............................................................. 1 Equivalent Circuits..................................................................... 12 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 13 Product Highlights ........................................................................... 1 Theory of Operation ...................................................................... 16 Revision History ............................................................................... 2 Using the AD9410 ...................................................................... 16 Specifications..................................................................................... 3 Analog Input ............................................................................... 16 DC Specifications ......................................................................... 3 Digital Outputs ........................................................................... 16 Switching Specifications .............................................................. 4 Clock Outputs (DCO, DCO).................................................... 16 Digital Specifications ................................................................... 4 Voltage Reference ....................................................................... 17 AC Specifications.......................................................................... 5 Timing ......................................................................................... 17 Absolute Maximum Ratings............................................................ 7 Data Sync (DS) ........................................................................... 17 Explaination of Test Levels.......................................................... 7 Outline Dimensions ....................................................................... 19 ESD Caution.................................................................................. 7 Ordering Guide .......................................................................... 19 REVISION HISTORY 7/07Rev. 0 to Rev. A 10/00Revision 0: Initial Version Updated Format..................................................................Universal Deleted 80-Lead LQFP EP ...............................................Universal Added 80-Lead TQFP EP.................................................Universal Changes to Figure 1 and General Description ............................. 1 Changes to Table 2 and Table 3....................................................... 4 Changes to Figure 2.......................................................................... 6 Changes to Note 1............................................................................. 7 Changes to Figure 3 and Table 6..................................................... 8 Changes to Terminology Section.................................................. 10 Changes to Figure 6........................................................................ 12 Deleted Evaluation Board Section................................................ 14 Renamed Encode Input Section, Clock Input Section and DCO Changes to Clock Input Section, Clock Outputs (DCO, ) Section, Figure 26, and Figure 27 ................................................. 16 Changes to Data Sync (DS) Section ............................................. 17 Changes to Figure 29...................................................................... 18 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 Rev. 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