PI6CG18201ZDIE Diodes Incorporated

A product Line of Diodes Incorporated PI6CG18201 Very Low Power 2-Output PCIe Clock Generator With On-chip Termination Features Description 1.8V supply voltage e PTh I6CG18201 is an 2-output very low power PCIe Gen1/Gen2/ Crystal/CMOS input: 25 MHz Gen3/ Gen4 clock generator. It uses 25MHz crystal or CMOS ref- 2 differential low power HCSL outputs with on-chip erence as an input to generate the 100MHz low power differential termination HCSL outputs with on-chip terminations. The on-chip termina - tion can save 8 external resistors and make layout easier. An ad- Individual output enable ditional buffered reference output is provided to serve as a low Reference CMOS output noise reference for other circuitry. Programmable Slew rate and output amplitute for each output It uses Diodes proprietary PLL design to achieve very low jitter Differential outputs blocked until PLL is locked that meets PCIe Gen1/Gen2/Gen3/Gen4 requirements. It also provides various options such as different slew rate and ampli - Selectable 0%, -0.25% or -0.5% spread on differential outputs tude through strapping pins or SMBUS so that users can config - Strapping pins or SMBus for configuration ure the device easily to get the optimized performance for their 3.3V tolerant SMBus interface support individual boards. The device also supports selectable spread- Very low jitter outputs spectrum options to reduce EMI for various applications. Differential cycle-to-cycle jitter <50ps Differential output-to-output skew <50ps PCIe Gen1/Gen2/Gen3/Gen4 compliant CMOS REFOUT phase jitter is < 1.5ps RMS Packaging (Pb-free & Green): 24-lead 44mm TQFN Pin Configuration 24 23 22 21 20 19 1 Q1- XTAL IN/CLK 18 Q1+ XTAL OUT 2 17 V 3 VDDA DD OSC 16 GND 4 SADR/REFOUT 15 GNDA 5 Q0- GND REFOUT 14 6 Q0+ GND DIG 13 7 8 9 10 11 12 www.diodes.com Nov 2017 PI6CG18201 1 Document Number DS39996 Rev 4-2 Diodes Incorporated V DD DIG GND XTAL SCLK SS SEL TRI SDATA PD GND GND V DDO V DDO OE0 OE1 A product Line of Diodes Incorporated PI6CG18201 Block Diagram REFOUT OE 1:0 Q1 XTAL IN/CLK OSC PLL XTAL OUT SS Q0 SCLK SDATA SADR CTRL SS SEL TRI LOGIC PD www.diodes.com Nov 2017 PI6CG18201 2 Document Number DS39996 Rev 4-2 Diodes Incorporated