CY2544
CY2546
PRELIMINARY
Quad PLL Programmable Clock Generator with
Spread Spectrum
Features Benefits
Multiple high-performance PLLs allow synthesis of
Four fully integrated phase-locked loops (PLLs)
unrelated frequencies
Input Frequency range:
Nonvolatile programming for customized PLL frequencies,
External crystal: 8 to 48 MHz
spread spectrum characteristics, drive strength, crystal load
capacitance, and output frequencies
External reference: 8 to 166 MHz clock
Two Spread Spectrum capable PLLs with Linear or Lexmark
Wide operating output frequency range
profile for maximum EMI reduction
3 to 166 MHz
Spread Spectrum PLLs can be disabled or enabled
Programmable Spread Spectrum with Center and Down
separately
Spread option and Lexmark modulation profile
PLLs can be programmed for system frequency margin
Two VDD core voltage options:
tests
2.5V, 3.0V, and 3.3V for CY2544
Meets critical timing requirements in complex system
designs
1.8V for CY2546
Suitable for PC, consumer, and networking applications
Selectable output voltages:
Ability to synthesize standard frequencies with ease
2.5V, 3.0V, and 3.3V for CY2544
Application compatibility in standard and low-power
1.8V for CY2546
systems
Frequency Select feature with option to select eight different
frequencies
Low jitter, high accuracy outputs
Up to nine clock outputs
Programmable output drive strength
Glitch-free outputs while frequency switching
24-pin QFN package
Commercial and Industrial temperature ranges
Block Diagram
EXCLKIN
4of6
Crossbar
CLK1
Switch
Bank
CLK2
XIN 1
Output
OSC PLL1 CLK3
XOUT
Dividers
CLK4
Bank
and
CLK5
2
Drive
FS0
PLL2 CLK6
Strength
MUX
FS1
CLK7
and
Control
FS2 Bank
Control
CLK8
3
Logic
PLL3
CLK9
(SS)
PLL4
(SS)
PD#/OE
SSON
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 001-12563 Rev. *A Revised February 28, 2007
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CY2544
CY2546
PRELIMINARY
Pin Configuration
24 23 22 21 20 19 24 23 22 21 20 19
1 18
GND GND 1 18
GND GND
2 17 2 17
CLK1 CLK8 CLK1 CLK8
3 16
VDD_CLK_B1 VDD_CLK_B3 3 16 VDD_CLK_B3
VDD_CLK_B1
CY2544
CY2546
24LD QFN
24LD QFN
PD#OE 4 15 4 15
CLK7/SSON PD#OE CLK7/SSON
5 14 VDD_CLK_B2
NC 5 14 VDD_CLK_B2
VDD_CORE
6 13 6 13
CLK2 CLK6 CLK2 CLK6
7 8 9 10 11 12
7 8 9 10 11 12
Pin Description - CY2544 (2.5V, 3.0V or 3.3V VDD)
Pin Number Name I/O Description
1 GND Power Power Supply Ground for Core
2 CLK1 Output Programmable Output Clock
3 VDD_CLK_B1 Power 2.5V/3.0V/3.3V Power Supply for Output Bank1 (CLK1, CLK2,
CLK3) output
4 PD#/OE Input Power Down or Output Enable
5 NC NC No Connect
6 CLK2 Output Programmable Output Clock
7 GND Power Power Supply Ground for Output Bank 1
8 CLK3/FS0 Output/Input Multifunction Programmable pin,CLK3 Output Clock or Frequency
Select pin FS0
9 PD#/OE/FS1 Input Multifunction Programmable pin, Power Down, Output Enable or
Frequency Select pin FS1
10 CLK4/FS2 Output/Input Multifunction Programmable pin, CLK4 Output or Frequency Select
input pin FS2
11 CLK5 Output Programmable Output Clock
12 GND Power Power Supply Ground for Output Bank 2
13 CLK6 Output Programmable Output Clock
14 VDD_CLK_B2 Power 2.5V/3.0V/3.3V Power Supply for Output Bank2 (CLK4, CLK5,
CLK6) output
15 CLK7/SSON Output/Input Multifunction Programmable pin, CLK7 Output or SSON input
16 VDD_CLK_B3 Power 2.5V/3.0V/3.3V Power Supply for Output Bank3 (CLK7, CLK8,
CLK9) output
17 CLK8 Output Programmable Output Clock
18 GND Power Power Supply Ground for Output Bank 3
Document #: 001-12563 Rev. *A Page 2 of 11
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CLK3/FS0
CLK4/FS2
CLK3/FS0
CLK4/FS2
XIN
XOUT
VDD
XIN
XOUT
_
VDD CORE
EXCLKIN
EXCLKIN
CLK9
GND
CLK9
GND
PD#/OE/FS1
PD#/OE/FS1
GND
GND
GND
CLK5
G
5
ND
CLK