Product Information

74HC4046AD

74HC4046AD electronic component of NXP

Datasheet
74HC4046AD MOVED TO 404783DB SMD

Manufacturer: NXP
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1: USD 1.6809 ea
Line Total: USD 1.6809

0 - Global Stock
Ships to you by
Fri. 29 Mar
MOQ: 1  Multiples: 1
Pack Size: 1
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0 - Global Stock


Ships to you by Fri. 29 Mar

MOQ : 1
Multiples : 1
1 : USD 1.6809
2 : USD 1.5208
3 : USD 1.2007
4 : USD 1.0406
5 : USD 1.0005

     
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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4046A Phase-locked-loop with VCO 1997 Nov 25 Product specication Supersedes data of September 1993 File under Integrated Circuits, IC06Philips Semiconductors Product specication Phase-locked-loop with VCO 74HC/HCT4046A FEATURES provided at pin 10 (DEM ). In contrast to conventional OUT techniques where the DEM voltage is one threshold OUT Low power consumption voltage lower than the VCO input voltage, here the Centre frequency of up to 17 MHz (typ.) at V = 4.5 V CC DEM voltage equals that of the VCO input. If OUT DEM is used, a load resistor (R ) should be connected Choice of three phase comparators: EXCLUSIVE-OR OUT S from DEM to GND if unused, DEM should be left edge-triggered JK flip-flop OUT OUT open. The VCO output (VCO ) can be connected edge-triggered RS flip-flop OUT directly to the comparator input (COMP ), or connected IN Excellent VCO frequency linearity via a frequency-divider. The VCO output signal has a duty VCO-inhibit control for ON/OFF keying and for low factor of 50% (maximum expected deviation 1%), if the standby power consumption VCO input is held at a constant DC level. A LOW level at the inhibit input (INH) enables the VCO and demodulator, Minimal frequency drift while a HIGH level turns both off to minimize standby Operating power supply voltage range: power consumption. VCO section 3.0 to 6.0 V digital section 2.0 to 6.0 V The only difference between the HC and HCT versions is the input level specification of the INH input. This input Zero voltage offset due to op-amp buffering disables the VCO section. The sections of the comparator Output capability: standard are identical, so that there is no difference in the I category: MSI. CC SIG (pin 14) or COMP (pin 3) inputs between the HC IN IN and HCT versions. GENERAL DESCRIPTION Phase comparators The 74HC/HCT4046A are high-speed Si-gate CMOS The signal input (SIG ) can be directly coupled to the IN devices and are pin compatible with the 4046 of the self-biasing amplifier at pin 14, provided that the signal 4000B series. They are specified in compliance with swing is between the standard HC family input logic levels. JEDEC standard no. 7A. Capacitive coupling is required for signals with smaller The 74HC/HCT4046A are phase-locked-loop circuits that swings. comprise a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3) Phase comparator 1 (PC1) with a common signal input amplifier and a common This is an EXCLUSIVE-OR network. The signal and comparator input. comparator input frequencies (f ) must have a 50% duty i The signal input can be directly coupled to large voltage factor to obtain the maximum locking range. The transfer signals, or indirectly coupled (with a series capacitor) to characteristic of PC1, assuming ripple (f =2f ) is r i small voltage signals. A self-bias input circuit keeps small V voltage signals within the linear region of the input CC suppressed, is: V =() ----------- DEMOUT SIGIN COMPIN amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO where V is the demodulator output at pin 10 DEMOUT linearity is achieved by the use of linear op-amp V =V (via low-pass filter). DEMOUT PC1OUT techniques. V CC The VCO requires one external capacitor C1 (between The phase comparator gain is:K= -----------()Vr . p C1 and C1 ) and one external resistor R1 (between A B The average output voltage from PC1, fed to the VCO R and GND) or two external resistors R1 and R2 1 input via the low-pass filter and seen at the demodulator (between R and GND, and R and GND). Resistor R1 1 2 output at pin 10 (V ), is the resultant of the phase DEMOUT and capacitor C1 determine the frequency range of the differences of signals (SIG ) and the comparator input IN VCO. Resistor R2 enables the VCO to have a frequency (COMP ) as shown in Fig.6. The average of V is offset if required. IN DEMOUT 1 equal to V when there is no signal or noise at 2 CC The high input impedance of the VCO simplifies the design SIG and with this input the VCO oscillates at the centre IN of low-pass filters by giving the designer a wide choice of frequency (f ). Typical waveforms for the PC1 loop locked resistor/capacitor ranges. In order not to load the low-pass o at f are shown in Fig.7. filter, a demodulator output of the VCO input voltage is o 1997 Nov 25 2

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
FR9
Freescale
FREESCALE SEMI
Freescale Semicon
FREESCALE SEMICONDUC
Freescale Semiconductor
Freescale Semiconductor - NXP
NXP
NXP Freescale
NXP (FREESCALE)
NXP / Freescale
NXP SEMI
NXP Semicon
NXP SEMICONDUCTOR
NXP Semiconductors
NXP USA Inc.
PH3
PHI

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