MCF51JE256CLK

Freescale Semiconductor Document NumberDocument Number: MCF51JE256: MCF51JE256 ReRevv.. 4, 08/2012 4, 08/2012 Data Sheet: Advanced Information An Energy-Efficient Solution from Freescale MCF51JE256/128 MCF51JE256/128 The MCF51JE256 series devices are members of the low-cost, low-power, high-performance ColdFire V1 family of 32-bit microcontrollers (MCUs). Not all features are available in all devices or packages see Table 1 for a comparison of features by device. 80-LQFP 100-LQFP 81-BGA 104-BGA 12mm x 12mm 14mm x 14mm 10mm x 10mm 10mm x 10mm Peripherals 32-Bit ColdFire V1 Central Processor Unit (CPU) USB Dual-role USB On-The-Go (OTG) device, supports USB in either Up to 50.33 MHz ColdFire CPU above 2.4 V and 40 MHz CPU above 2.1 V device, host or OTG configuration. On-chip transceiver and 3.3V regulator and 20 MHz CPU above 1.8 V across temperature range of -40C to help save system cost, fully compliant with USB Specification 2.0. Allows 105C. control, bulk, interrupt and isochronous transfers. ColdFire Instruction Set Revision C (ISA C). SCIx Two serial communications interfaces with optional 13-bit break 32-bit multiply and accumulate (MAC) supports signed or unsigned integer option to connect Rx input to PRACMP output on SCI1 and SCI2 High or signed fractional inputs. current drive on Tx on SCI1 and SCI2 wake-up from stop3 on Rx edge. On-Chip Memory SPI1 Serial peripheral interface with 32-bit FIFO buffer 16-bit or 8-bit 256 K Flash comprised of two independent 128 K flash arrays data transfers full-duplex or single-wire bidirectional double-buffered read/program/erase over full operating voltage and temperature allows transmit and receive master or slave mode MSB-first or LSB-first shifting. interrupt processing while programming. SPI2 Serial peripheral interface with full-duplex or single-wire 32 KB System Random-access memory (RAM). bidirectional Double-buffered transmit and receive Master or Slave Security circuitry to prevent unauthorized access to RAM and Flash mode MSB-first or LSB-first shifting. contents. IIC Up to 100 kbps with maximum bus loading Multi-master operation Programmable slave address Interrupt driven byte-by-byte data transfer Power-Saving Modes supports broadcast mode and 10-bit addressing. Two ultra-low power stop modes. Peripheral clock enable register can CMT Carrier Modulator timer for remote control communications. disable clocks to unused modules to reduce currents. Carrier generator, modulator and driver for dedicated infrared out (IRO). Time of Day (TOD) Ultra low-power 1/4 sec counter with up to 64 sec Can be used as an output compare timer. timeout. TPMx Two 4-channel Timer/PWM Module Selectable input capture, Ultra-low power external oscillator that can be used in stop modes to output compare, or buffered edge- or center-aligned PWM on each provide accurate clock source to the TOD. 6 s typical wake up time from channel external clock input/pulse accumulator. stop3 mode. Mini-FlexBus Multi-function external bus interface with user Clock Source Options programmable chip selects and the option to multiplex address and data Oscillator (XOSC1) Loop-control Pierce oscillator 32.768 kHz crystal or lines. ceramic resonator dedicated for TOD operation. PRACMP Analog comparator with selectable interrupt compare option Oscillator (XOSC2) for high frequency crystal input for MCG reference to to programmable internal reference voltage operation in stop3. be used for system clock and USB operations. ADC12 12-bit Successive approximation ADC with up to12 Multipurpose Clock Generator (MCG) PLL and FLL precision trimming single-ended channels internal bandgap reference channel operation in of internal reference allows 0.2% resolution and typical +0.5% to -1% stop3 fully functional from 3.6V to 1.8V. deviation over temperature and voltage supports CPU frequencies up to PDB Programmable delay block with 16-bit counter and modulus and 50 MHz. prescale to set reference clock to bus divided by 1 to bus divided by 2048 System Protection 8 trigger outputs for ADC module provides periodic coordination of ADC Watchdog computer operating properly (COP) reset with option to run from sampling sequence with sequence completion interrupt Back-to-Back dedicated 1 kHz internal clock source or bus clock. mode and Timed mode. Low-voltage detection with reset or interrupt selectable trip points DAC 12-bit resolution DAC configurable settling time. separate low voltage warning with optional interrupt selectable trip points. Input/Output Illegal opcode and illegal address detection with reset. Up to 68 GPIOs and 1 output-only pin. Flash block protection for each array to prevent accidental write/erasure. Voltage Reference output (VREFO). Hardware CRC to support fast cyclic redundancy checks. Dedicated infrared output pin (IRO) Development Support withhigh current sink capability. Integrated ColdFire DEBUG Rev B+ interface with single wire BDM Up to 16 KBI pins with selectable connection supports same electrical interface used by the S08 family polarity. debug modules. Up to 16 pins of rapid general purpose Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1 I/O (RGPIO). data). On-chip trace buffer provides programmable start/stop recording conditions. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2009-2012. All rights reserved.Contents Figure 13.Timer External Clock . 36 Table of Contents Figure 14.Timer Input Capture Pulse . 36 1 Features 4 Figure 15.SPI Master Timing (CPHA = 0) . 38 2 Pinouts and Pin Assignments 7 Figure 16.SPI Master Timing (CPHA = 1) . 38 2.1 104-Pin MAPBGA 7 Figure 17.SPI Slave Timing (CPHA = 0) 39 2.2 100-Pin LQFP .8 Figure 18.SPI Slave Timing (CPHA = 1) 39 2.3 81-Pin MAPBGA .9 Figure 19.Typical VREF Output vs Temperature 42 2.4 80-Pin LQFP 10 Figure 20.Typical VREF Output vs V . 43 DD 2.5 Pin Assignments 11 3 Preliminary Electrical Characteristics 15 3.1 Parameter Classification 15 List of Tables 3.2 Absolute Maximum Ratings .15 3.3 Thermal Characteristics 16 Table 1. MCF51JE Features by MCU and Package 4 3.4 ESD Protection Characteristics .18 Table 2. MCF51JE256/128 Functional Units 5 3.5 DC Characteristics 18 Table 2-3.Package Pin Assignments . 11 3.6 Supply Current Characteristics .21 Table 4. Parameter Classifications 15 3.7 PRACMP Electricals .24 Table 5. Absolute Maximum Ratings . 16 3.8 12-bit DAC Electricals 24 Table 6. Thermal Characteristics 17 3.9 ADC Characteristics .26 Table 7. ESD and Latch-up Test Conditions . 18 3.10 MCG and External Oscillator (XOSC) Characteristics .29 Table 8. ESD and Latch-Up Protection Characteristics . 18 3.11 Mini-FlexBus Timing Specifications .32 Table 9. DC Characteristics 19 3.12 AC Characteristics 34 Table 10.Supply Current Characteristics 21 3.12.1 Control Timing 34 Table 11.Stop Mode Adders 22 3.12.2 TPM Timing 36 Table 12.PRACMP Electrical Specifications . 24 3.13 SPI Characteristics 37 Table 13.DAC 12LV Operating Requirements 24 3.14 Flash Specifications .40 Table 14.DAC 12-Bit Operating Behaviors . 25 3.15 USB Electricals .40 Table 15.12-bit ADC Operating Conditions 26 3.16 VREF Electrical Specifications .41 Table 16.12-bit SAR ADC Characteristics full operating range 4 Ordering Information 44 (VREFH = VDDAD, VREFL = VSSAD) 28 4.1 Part Numbers 44 Table 17.MCG (Temperature Range = 40 to 105C Ambient) . 29 4.2 Package Information .44 Table 18.XOSC (Temperature Range = 40 to 105C Ambient) 31 4.3 Mechanical Drawings 44 Table 19.Mini-FlexBus AC Timing Specifications 32 5 Revision History .45 Table 20.Control Timing . 34 Table 21.TPM Input Timing 36 Table 22.SPI Timing 37 Table 23.Flash Characteristics 40 List of Figures Table 24.Internal USB 3.3 V Voltage Regulator Characteristics 40 Figure 1.MCF51JE256/128 Block Diagram . 3 Table 25.VREF Electrical Specifications 41 Figure 2.104-Pin MAPBGA . 7 Table 26.VREF Limited Range Operating Behaviors . 42 Figure 3.100-Pin LQFP 8 Table 27.Orderable Part Number Summary 44 Figure 4.81-Pin MAPBGA 9 Table 28.Package Descriptions . 44 Figure 5.80-Pin LQFP Pinout 10 Table 29.Revision History 45 Figure 6.Stop IDD versus Temperature . 23 Figure 7.Offset at Half Scale vs Temperature 26 Figure 8.ADC Input Impedance Equivalency Diagram . 28 Figure 9.Mini-FlexBus Read Timing . 33 Figure 10.Mini-FlexBus Write Timing 33 Figure 11.Reset Timing . 35 Figure 12.IRQ/KBIPx Timing . 35 MCF51JE256 Datasheet, Rev. 4 2 Freescale Semiconductor