Document Number: IMX8DXIEC NXP Semiconductors Rev. 0, 05/2020 Data Sheet: Technical Data MIMX8UXnCVLFZAC i.MX 8DualX Industrial Applications Processors Package Information 21 x 21 mm package case outline Ordering Information See Section 1.1Table 2 on page 5 1 Introduction 1 1 Introduction 1.1 Ordering Information 5 1.2 System Controller Firmware (SCFW) Requirements5 This data sheet contains specifications for the 1.3 Related resources 5 2 Architectural Overview . 6 i.MX 8DualX processor, which, along with the 2.1 Block Diagram . 7 i.MX 8QuadXPlus and 8DualXPlus processors, 3 Modules List . 8 3.1 Special Signal Considerations 14 comprise the i.MX 8X Family (for i.MX 8QuadXPlus 3.2 Recommended Connections for Unused Interfaces14 and 8DualXPlus specifications, see i.MX 8QuadXPlus 4 Electrical characteristics . 15 and 8DualXPlus Industrial Processors 4.1 Chip-level conditions . 15 4.2 Power supplies requirements and restrictions 25 IMX8QXPIEC ). The i.MX 8X processors consist of 4.3 PLL electrical characteristics . 28 three to five Arm cores (two to four Arm Cortex -A35 4.4 On-chip oscillators . 31 4.5 I/O DC Parameters 33 and one Cortex -M4F). All devices include separate 4.6 I/O AC Parameters 41 GPU and VPU subsystems as well as a failover-ready 4.7 Output Buffer Impedance Parameters 42 display controller. Advanced multicore audio processing 4.8 System Modules Timing 47 4.9 General-Purpose Media Interface (GPMI) Timing. 51 is supported by the Arm cores and a high performance 4.10 External Peripheral Interface Parameters . 60 Tensilica HiFi 4 DSP for pre- and post-audio 4.11 Analog-to-digital converter (ADC) 104 5 Boot mode configuration 108 processing as well as voice recognition. The i.MX 8X 5.1 Boot mode configuration pins . 108 Family supports up to three displays with multiple 5.2 Boot devices interfaces allocation 108 display output options, including parallel, MIPI-DSI, 6 Package information and contact assignments 110 6.1 FCPBGA, 21 x 21 mm, 0.8 mm pitch . 110 and LVDS. Memory interfaces for this device include: 7 Release Notes . 126 LPDDR4 DDR3L 2 Quad SPI or 1 Octal SPI (FlexSPI) NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2018-2020 NXP B.V.Introduction eMMC 5.1, RAW NAND, and SD 3.0 A wide range of peripheral I/Os such as CAN, parallel or MIPI CSI camera input, Gigabit Ethernet, USB 2.0 OTG, USB 3.0 (8QuadXPlus/8DualXPlus only), ADC, and PCIe 3.0 provide impressive flexibility. The i.MX 8DualX processor offers numerous advanced features as shown in this table. Table 1. i.MX 8DualX advanced features Function Feature Multicore architecture provides AArch64 for 64-bit support and new architectural features 2 Cortex-A35 and 1 Cortex-M4F AArch32 for full backward compatibility with ARMv7 cores Cortex-A35 cores support ARM virtualization extensions. Cortex-M4F cores for real-time applications Graphics Processing Unit (GPU) 4 Vec4 shaders with 16 execution units optimized for lower memory bandwidth Supports OpenGL 3.0, 2.1, OpenGL ES 3.1, 3.0, 2.0, and 1.1 OpenCL 1.2 Full Profile and 1.1 OpenVG 1.1 and Vulkan High-performance 2D Blit Engine Video Processing Unit (VPU) H.264 decode (4Kp30) WMV9/VC-1 imple decode MPEG 1 and 2 decode AVS decode MPEG4.2 ASP, H.263, Sorenson Spark decode Divx 3.11 including GMC decode ON2/Google VP6/VP8 decode RealVideo 8/9/10 decode JPEG and MJPEG decode H.264 encode (1080p30) Tensilica HiFi 4 DSP for pre- and 640 MHz post-processing Fixed-point and vector-floating-point support 32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and 64 KB of TCM) i.MX 8DualX Industrial Applications Processors, Rev. 0, 05/2020 2 NXP Semiconductors