AS4C128M8D3B-12BCN Alliance Memory

AS4C128M8D3B-12BIN AS4C128M8D3B-12BCN Revision History 1Gb DDR3 AS4C128M8D3 B 78ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Jan. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 85 - Rev.1.0 Jan.2018AS4C128M8D3B-12BIN AS4C128M8D3B-12BCN 128M x 8 bit DDR3 Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jan /2018) Features Overview JEDEC Standard Compliant The 1Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is Power supplies: V & V = +1.5V 0.075V DD DDQ internally configured as an eight bank DRAM. Operating temperature range: The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 bank : T = 0~95 C - Commercial C devices. These synchronous devices achieve high : T = -40~95 C - Industrial C speed double-data-rate transfer rates of up to 1600 Mb/ Supports JEDEC clock jitter specification sec/pin for general applications. Fully synchronous operation The chip is designed to comply with all key DDR3 DRAM Fast clock rate: 800MHz key features and all of the control and address inputs are synchronized with a pair of externally supplied differential Differential Clock, CK & CK clocks. Inputs are latched at the cross point of differential Bidirectional differential data strobe clocks (CK rising and CK falling). All I/Os are synchronized - DQS & DQS with differential DQS pair in a source synchronous fashion. 8 internal banks for concurrent operation These devices operate with a single 1.5V 0.075V power 8n-bit prefetch architecture supply and are available in BGA packages. Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 8 x 10.5 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Org Max Clock (MHz) Product part No Package 800 128M x 8 Commercial 0C to 95C 78-ball FBGA AS4C128M8D3B-12BCN 800 128M x 8 Industrial -40C to 95C 78-ball FBGA AS4C128M8D3B-12BIN Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RCD RP 800 MHz 11 13.75 13.75 DDR3-1600 Confidential - 2 of 85 - Rev.1.0 Jan.2018