Product Information

AS7C1024B-15JCNTR

AS7C1024B-15JCNTR electronic component of Alliance Memory

Datasheet
SRAM 1M, 5V, 15ns FAST 128K x 8 Asynch SRAM

Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 5.7092 ea
Line Total: USD 5.71

1 - Global Stock
Ships to you between
Thu. 09 May to Mon. 13 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
476 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1

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AS7C1024B-15JCNTR
Alliance Memory

1 : USD 5.221
10 : USD 4.8185
100 : USD 4.324
250 : USD 4.3125
500 : USD 4.1055
1000 : USD 3.8985
2000 : USD 3.841
5000 : USD 3.7605
10000 : USD 3.657

     
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RoHS - XON
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AS7C1 024B 5V 128K X 8 HIGH SPEED CMOS SRAM Revision History AS7C1024B Revision Details Date Rev 1.0 Preliminary datasheet prior to 2004 Rev 1.1 Die Revision A to B March 2004 Rev 2.0 PCN issued yield issues with industrial temperature TJ = SOJ 300 mil-10/12ns May 2015 *Please note we will still offer 10/12/15/20 ns address access speed options in commercial temperatures in other packages Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 0 Rev2.0 May 2015 March 2004 AS7C1024B 5V 128K X 8 CMOS SRAM Features - 300 mil SOJ Industrial and commercial temperatures - 400 mil SOJ Organization: 131,072 words x 8 bits - 8 20mm TSOP 1 High speed - 8 x 13.4mm sTSOP 1 - 10/12/15/20 ns address access time ESD protection 2000 volts - 5/6/7/8 ns output enable access time Latch-up current 200 mA Low power consumption: ACTIVE - 605 mW / max 10 ns Low power consumption: STANDBY - 55 mW / max CMOS 6T 0.18u CMOS technology Easy memory expansion with CE1, CE2, OE inputs Pin arrangement TTL/LVTTL-compatible, three-state I/O 32-pin SOJ (300 mil) 32-pin JEDEC standard packages 32-pin SOJ (400 mil) Logic block diagram V NC 1 32 CC A15 A16 2 31 CE2 A14 3 30 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 V CC A11 A4 8 25 A3 9 24 OE GND A10 A2 10 23 A1 11 22 CE1 Input buffer A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 A0 I/O2 15 18 I/O4 GND 16 17 I/O3 A1 I/O7 A2 512 x 256 x 8 A3 32-pin (8 x 20mm) TSOP I A4 32-pin (8 x 13.4mm) sTSOP1 Array A5 (1,048,576) A11 1 32 OE A6 A9 2 31 A10 A7 I/O0 A8 3 30 CE1 A8 A13 4 29 I/O7 5 28 WE I/O6 6 27 CE2 I/O5 7 A15 26 I/O4 WE Column decoder 8 25 I/O3 V CC Control OE 9 24 GND NC 10 A16 23 I/O2 circuit CE1 11 22 A14 I/O1 CE2 12 21 A12 I/O0 13 20 A7 A0 14 19 A6 A1 18 15 A5 A2 17 16 A4 A3 Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access 56 7 8 ns time Maximum Operating Current 110 100 90 80 mA Maximum CMOS standby Current 10 10 10 10 mA May 2015 v2.0 Alliance Memory Inc P. 1 of 9 Copyright Alliance Memory Inc. All rights reserved. Row decoder A9 A10 A11 A12 A13 A14 A15 A16 Sense amp AS7C1024B AS7C1024B

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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