ADSP-21375KSWZ-2B

SHARC Processor ADSP-21371/ADSP-21375 SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor ADSP-21371S/PDIF-compatible digital audio optimized for high performance audio processing receiver/transmitter Single-instruction, multiple-data (SIMD) computational ADSP-213718 dual data line serial ports that operate at up architecture to 33 Mbps on each data line each has a clock, frame On-chip memory, ADSP-213711M bits of on-chip SRAM sync, and two data lines that can be configured as either a and 4M bits of on-chip mask-programmable ROM receiver or transmitter pair On-chip memory, ADSP-213750.5M bits of on-chip 16 PWM outputs configured as four groups of four outputs SRAM and 2M bits of on-chip mask-programmable ROM ROM-based security features include JTAG access to memory permitted with a 64-bit key Code compatible with all other members of the SHARC family Protected memory regions that can be assigned to limit The ADSP-21371/ADSP-21375 processors are available with a access under program control to sensitive code 200/266 MHz core instruction rate with unique audiocen- PLL has a wide variety of software and hardware multi- tric peripherals such as the digital applications interface, plier/divider ratios S/PDIF transceiver, serial ports, precision clock generators, and more. For complete ordering information, see Order- Available in a 208-lead LQFP EP package ing Guide on Page 56. Internal Memory SIMD Core Block 0 Block 1 Block 2 Block 3 RAM/ROM RAM/ROM RAM RAM Instruction 5 stage Cache Sequencer B2D B0D B1D B3D 64-BIT 64-BIT 64-BIT 64-BIT DAG1/2 Timer S DMD 64-BIT DMD 64-BIT PEx PEy Core Bus Internal Memory I/F Cross Bar PMD 64-BIT PMD 64-BIT IODO 32-BIT FLAGx/IRQx/ EPD BUS 48-BIT JTAG TMREXP PERIPHERAL BUS 32-BIT IOD1 32-BIT IOD0 BUS MTM/ DTCP PERIPHERAL BUS EP IDP/ S/PDIF CORE PCG TIMER PCG SPORT CORE PWM TWI SPI/B UART PDAP AMI SDRAM Tx/Rx FLAGS C-D 1-0 A-D 7-0 FLAGS 3-0 7-0 DPI Routing/Pins External Port Pin MUX DAI Routing/Pins External DPI Peripherals DAI Peripherals Peripherals Port Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Technical Support www.analog.comADSP-21371/ADSP-21375 TABLE OF CONTENTS Summary ............................................................... 1 Package Information ............................................ 18 Dedicated Audio Components ................................. 1 Maximum Power Dissipation ................................. 18 General Description ................................................. 3 Absolute Maximum Ratings ................................... 18 SHARC Family Core Architecture ............................ 4 ESD Sensitivity ................................................... 18 Family Peripheral Architecture ................................ 6 Timing Specifications ........................................... 18 I/O Processor Features ......................................... 10 Output Drive Currents ......................................... 49 System Design .................................................... 10 Test Conditions .................................................. 49 Development Tools ............................................. 11 Capacitive Loading .............................................. 49 Additional Information ........................................ 12 Thermal Characteristics ........................................ 50 Related Signal Chains .......................................... 12 208-Lead LQFP EP Pinout ....................................... 51 Pin Function Descriptions ....................................... 13 Package Dimensions ............................................... 55 ADSP-21371/ADSP-21375 Specifications .................... 16 Automotive Products .............................................. 56 Operating Conditions .......................................... 16 Ordering Guide ..................................................... 56 Electrical Characteristics ....................................... 17 REVISION HISTORY 4/13Rev. C to Rev. D Added 1.0 V, 200 MHz specifications to the following timing specifications. Corrected Extended Precision Normal or Instruction Word (48 bits) ADSP-21375 Internal Memory Space .................7 Clock Input ............................................................21 Updated Development Tools ..................................... 11 Precision Clock Generator (Direct Pin Routing) .............26 Added section Related Signal Chains ...........................12 SDRAM Interface Timing ..........................................28 Revised MS pin description in Memory ReadBus Master .......................................29 1-0 Pin Function Descriptions ........................................ 13 Memory WriteBus Master ......................................31 Corrected EMU pin Type from O/T (pu) to O (O/D) (pu) in Serial Ports ............................................................33 Pin Function Descriptions ........................................ 13 Input Data Port (IDP) ..............................................38 Corrected T specifications in JUNCTION S/PDIF Transmitter Input Data Timing ........................42 Operating Conditions .............................................. 16 S/PDIF Receiver ......................................................43 Added footnote 3 to Table 25 in Memory ReadBus Master ....................................... 29 SPI InterfaceSlave .................................................45 Updated Serial Ports timing parameter data in Serial Ports External Clock ....................................................... 33 Updated Serial Ports timing parameter data in Serial Ports Internal Clock ........................................................ 34 Changed Max values in Table 33 in Pulse-Width Modulation Generators (PWM) ................................................. 40 Updated timing parameters in Table 37 and in Figure 31 in SPI InterfaceMaster .............................................. 44 Rev. D Page 2 of 56 April 2013