CYS25G0101DX
SONET OC-48 Transceiver
SONET OC-48 Transceiver
Features Functional Description
SONET OC-48 operation The CYS25G0101DX SONET OC-48 Transceiver is a
communications building block for high speed SONET data
Bellcore and ITU jitter compliance
communications. It provides complete parallel-to-serial and
serial-to-parallel conversion, clock generation, and clock and
2.488 GBaud serial signaling rate
data recovery operations in a single chip optimized for full
Multiple selectable loopback or loop through modes
SONET compliance.
Single 155.52 MHz reference clock
Transmit Path
Transmit FIFO for flexible data interface clocking
New data is accepted at the 16-bit parallel transmit interface at
a rate of 155.52 MHz. This data is passed to a small integrated
16-bit parallel-to-serial conversion in transmit path
FIFO to enable flexible transfer of data between the SONET
Serial-to-16-bit parallel conversion in receive path
processor and the transmit serializer. As each 16-bit word is read
from the transmit FIFO, it is serialized and sent out to the high
Synchronous parallel interface
speed differential line driver at a rate of 2.488 Gbits per second.
LVPECL compliant
HSTL compliant
Receive Path
Internal transmit and receive phase-locked loops (PLLs) As serial data is received at the differential line receiver, it is
passed to a clock and data recovery (CDR) PLL that extracts a
Differential CML serial input
precision low jitter clock from the transitions in the data stream.
50 mV input sensitivity
This bit rate clock is used to sample the data stream and receive
100 internal termination and DC restoration
the data. Every 16-bit times, a new word is presented at the
receive parallel interface along with a clock.
Differential CML serial output
Source matched for 50 transmission lines (100 differential
Parallel Interface
transmission lines)
The parallel I/O interface supports high speed bus communica-
Direct interface to standard fiber optic modules
tions using HSTL signaling levels to minimize both power
consumption and board landscape. The HSTL outputs are
Less than 1.0W typical power
capable of driving unterminated transmission lines of less than
120-pin 14 mm 14 mm TQFP
70 mm and terminated 50 transmission lines of more than twice
that length.
Standby power saving mode for inactive loops
The CYS25G0101DX Transceivers parallel HSTL I/O can also
0.25 BiCMOS technology
be configured to operate at LVPECL signaling levels. This is
done externally by changing V , V and creating a simple
DDQ REF
Pb-free packages available
circuit at the termination of the transceivers parallel output
interface.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-02009 Rev. *O Revised October 24, 2013 CYS25G0101DX
Logic Block Diagram
(155.52 MHz) (155.52 MHz) (155.52 MHz)
TXCLKI REFCLK RXCLK
TXD[15:0] RXD[15:0]
FIFO_ERR TXCLKO
FIFO_RST
16
16
Input Output
Register Register
TX PLL
X16
16
Shifter
FIFO
16
Recovered
Bit-Clock
TX Bit-Clock
Shifter
RX CDR
Retimed
PLL
Data
Lock-to-Ref
LOOPTIME
DIAGLOOP
Lock-to-Data/
LINELOOP
Clock Control
LOOPA
Logic
OUT IN
PWRDN LOCKREF SD LFI RESET
Document Number: 38-02009 Rev. *O Page 2 of 22