XRT83VSH38 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT DECEMBER 2017 REV. 1.2.0 The on-chip clock synthesizer generates T1/E1/J1 GENERAL DESCRIPTION clock rates from a selectable external clock frequency The XRT83VSH38 is a fully integrated 8-channel and outputs a clock reference of the line rate chosen. short-haul line interface unit (LIU) that operates from Additional features include RLOS, a 16-bit LCV a 1.8V and a 3.3V power supply. Using internal counter for each channel, AIS, QRSS generation/ termination, the LIU provides one bill of materials to detection, TAOS, DMO, and diagnostic loopback operate in T1, E1, or J1 mode with minimum external modes. components. The LIU features are programmed through a standard parallel or serial microprocessor APPLICATIONS interface. EXARs LIU has patented high impedance T1 Digital Cross-Connects (DSX-1) circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a ISDN Primary Rate Interface power failure or when the LIU is powered off. Key CSU/DSU E1/T1/J1 Interface design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications T1/E1/J1 LAN/WAN Routers to ensure reliability without using relays. Public switching Systems and PBX Interfaces T1/E1/J1 Multiplexer and Channel Banks FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH38 T1/E1/J1 LIU (HOST MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 DRIVE 1 of 8 channels, CHANNEL n TAOS DMO n MONITOR TPOS n/TDATA n TTIP n QRSS HDB3/ TX FILTER TX/RX JITTER TIMING LINE TNEG n/CODES n PATTERN B8ZS & PULSE ATTENUATOR CONTROL DRIVER GENERATOR ENCODER SHAPER TCLK n TRING n TXON n Remote Digital Analog Loopback Loopback Loopback QRSS DETECTOR RCLK n HDB3/ TIMING & PEAK RTIP n TX/RX JITTER RNEG n/LCV n B8ZS DATA DETECTOR ATTENUATOR DECODER RECOVERY & SLICER RRING n RPOS n/RDATA n LOS AIS DETECTOR DETECTOR RLOS n TEST ICT HW/HOST PTS1 WR R/W PTS2 RD DS D 7:0 ALE-AS MICROPROCESSOR/SERIAL INTERFACE CONTROLLER CS PCLK/SCLK RDY DTACK/SDO A 7:0 /SDI INT RESET SER PAR 1XRT83VSH38 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.2.0 FIGURE 2. BLOCK DIAGRAM OF THE XRT83VSH38 T1/E1/J1 LIU (HARDWARE MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 TAOS n CLKSEL 2:0 DRIVE 1 of 8 channels, CHANNEL n TAOS MONITOR DMO n TPOS n/TDATA n QRSS HDB3/ TX FILTER TTIP n TX/RX JITTER TIMING LINE PATTERN B8ZS & PULSE TNEG n/CODES n ATTENUATOR CONTROL DRIVER GENERATOR ENCODER SHAPER TCLK n TRING n Remote Digital Analog TXON n Loopback Loopback Loopback QRSS DETECTOR HDB3/ TIMING & PEAK RCLK n TX/RX JITTER RTIP n B8ZS DATA DETECTOR RNEG n/LCV n ATTENUATOR DECODER RECOVERY & SLICER RRING n RPOS n/RDATA n LOOP1 n LOS AIS LOOP0 n DETECTOR DETECTOR RLOS n TEST ICT HW/HOST GAUGE RESET TRATIO JASEL1 SR/DR JASEL0 RXTSEL EQC 4:0 HARWARE CONTROL TCLKE TXTSEL TERSELR RCLKE RXMUTE XRES0 ATAOS RXRES1 2