XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR OCTOBER 2007 REV. 1.0.1 attempts to lock onto the incoming receive serial data GENERAL DESCRIPTION stream. Whenever the recovered clock frequency The XRT91L34 is a fully integrated quad channel deviates from the local reference clock frequency by multirate Clock and Data Recovery (CDR) device for more than approximately 500 ppm, the clock SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 recovery PLL will switch and lock back onto the local Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0 reference clock and declare a Loss of Lock. applications. The device provides Clock and Data Whenever a Loss of Lock or a Loss of Signal event Recovery (CDR) function by synchronizing its on-chip occurs, the CDR will continue to supply a recovered Voltage Controlled Oscillator (VCO) to the incoming clock (based on the local reference) to the framer/ serial data stream. The device internally monitors mapper device. When the SDEXT is de-asserted by Loss of Lock (LOL) conditions and automatically the optical module or when internal DLOS is mutes recovered data upon Loss of Signal (LOS) asserted, the receive serial data output will be forced conditions. to a logic zero state for the entire duration that a LOS condition is declared. This acts as a receive data CLOCK AND DATA RECOVERY OVERVIEW mute upon LOS function to prevent random noise The clock and data recovery (CDR) unit accepts the from being misinterpreted as valid incoming data. high speed NRZ serial data from the LVDS or When the SDEXT becomes active and the recovered Differential LVPECL receiver and generates a clock clock is determined to be within 500 ppm accuracy that is the same frequency as the incoming data. The with respect to the local reference source and LOS is CDR block uses a reference clock to train and no longer declared, the clock recovery PLL will switch monitor its clock recovery PLL. All four channels and lock back onto the incoming receive serial data share a single 77.76MHz or 19.44MHz reference stream. Figure 1 shows the block diagram of the clock. Upon startup, the PLL locks to the local XRT91L34. reference clock. Once this is achieved, the PLL FIGURE 1. BLOCK DIAGRAM OF XRT91L34 TEST RESET OUTCFG HOST /HW XRT91L34 0 DLOSDIS CDRREFSEL DLOSDIS /SDI SDI REFCLKP Global Control Block 1 19.44 / 77.76 MHz Serial Proccesor INT REFCLKN TTLREFCLK Interface CS LVDS/LVPECL LEVEL SELECT SCLK RCLKDIS0 SDO LVDS/LVPECL Output Drivers LVDS/LVPECL Input Drivers RECVD- RXDI0P RXDO0P 0 DATAOUT RXDATAIN 100 CDR RXDI0N RXDO0N 1 STS-12/3/1 or STM-4/1/0 RECVD- RXCLKO0P 0 CLKOUT Clock and Data RX LOOP Recovery RXCLKO0N FILTER 1 HOST MODE ONLY DLOSDIS LOL0 Channel Control Block CDRDIS0 DLOS DATA0RATE1 DATA0RATE0 SDEXT0 POL0 Channel 0 Channel 1 Channel 2 Channel 3 Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 APPLICATIONS SONET/SDH-based Transmission Systems Add/Drop Multiplexers Cross Connect Equipment ATM and Multi-Service Switches, Routers and Switch/Routers DSLAMS SONET/SDH Test Equipment DWDM Termination Equipment FEATURES Quad Channel CDR targeted for SONET STS-12/STS-3/STS-1 and SDH STM-4/STM-1/STM-0 Applications Selectable data rate operation between 622.08 Mbps, 155.52 Mbps, or 51.84 Mbps. Single-chip fully integrated solution containing quad-channel clock and data recovery (CDR) functions Optional flexibility to configure for LVDS or Differential LVPECL High Speed I/O Interface Internal 100 termination for the high speed LVDS/Differential LVPECL inputs included Utilizes reference clock frequency of either 19.44 MHz or 77.76 MHz Host mode serial microprocessor interface simplifies monitor and control, including LOS monitoring Diagnostics features include LOS monitoring in Host Mode and automatic recovered data mute upon LOS Loss of Lock Detect output for each channel Permits mixed data rate configuration of the four channels Independent power down control of unused channels for lower power operation Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications. Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V Differential LVPECL, and JESD 8-B LVTTL and LVCMOS standard. Operates with dual power supply of 1.8V core and 3.3V IO supply 90mW LVDS/ 350mW Differential LVPECL per channel Typical Power Dissipation Package: 14 x 14 x 1.4 mm 128-pin LQFP RoHS Compliant Lead-Free package availability ESD greater than 2kV on all pins 2