MD1821 High-Speed 4-Channel MOSFET Driver with Inverting Outputs Features General Description Inverting MOSFET Driver The MD1821 is a high-speed, 4-channel MOSFET driver designed to drive high-voltage P-channel and 6 ns Rise and Fall Time N-channel MOSFETs for medical ultrasound 2A Peak Output Source and Sink Currents applications and other applications requiring a high 1.8V to 5V Input CMOS Compatible output current for a capacitive load. The high-speed 5V to 10V Total Supply Voltage input stage of the MD1821 can operate from a 1.8V Smart Logic Threshold to 5V logic interface with an optimum operating input signal range of 1.8V to 3.3V. An adaptive threshold Low-jitter Design circuit is used to set the level translator switch Four Matched Channels threshold to the average of the input logic 0 and Drives Two P-channel and Two N-channel logic 1 levels. The input logic levels may be ground MOSFETs referenced even though the driver is putting out bipolar Outputs can Swing below Ground signals. The level translator uses a proprietary circuit, Low-inductance Quad Flat No-lead Package which provides DC coupling together with high-speed High-performance, Thermally Enhanced Package operation. The output stage of the MD1821 has separate power Applications connections, enabling the output signal L and H levels to be chosen independently from the supply voltages Medical Ultrasound Imaging used for the majority of the circuit. As an example, the Piezoelectric Transducer Drivers input logic levels may be 0V and 1.8V, the control logic Non-destructive Testing (NDT) may be powered by +5 and 5V and the output PIN Diode Driver L and H levels may be varied anywhere over the range of 5 to +5V. The output stage is capable of peak CCD Clock Driver/buffer currents of up to 2A, depending on the supply High-speed Level Translator voltages used and load capacitance present. The PE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Second, when PE is low, the outputs are disabled, with the A and C outputs high and the B and D outputs low. This assists in properly precharging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair. Package Type 16-lead QFN (Top view) 1 See Table 2-1 for pin information. 2017 Microchip Technology Inc. DS20005768A-page 1MD1821 Functional Block Diagrams MD1821 VDD VH PE OUTA INA OUTB INB OUTC INC OUTD IND VL GND VSS Simplified Block Diagram MD1821 VDD VH Level PE Shifter OUT A Level INA Shifter VSS VL VH VDD OUTB Level INB Shifter VSS VL VH VDD OUTC Level INC Shifter VSS VL VH VDD OUTD Level IND Shifter SUB GND VSS VL Detailed Block Diagram DS20005768A-page 2 2017 Microchip Technology Inc.