MEC1310-NU

MEC1310 Keyboard and Embedded Controller for Notebook PC - Two 16-Bit Timer/Counters Product Features - Integrated Full-Duplex Serial Port Interface 3.3V Operation with 5V Tolerant Buffers on PS/2 - Seventy-Three 8051 Interrupt Sources pins - Thirty-Two 8-Bit, Host/8051 Mailbox Regis- ACPI 1.0/2.0 PC99/PC2001 Compliant ters LPC Interface with Clock Run Support - Sixty-Four Maskable Hardware Wake-Up - Supports LPC Bus frequencies of 19.2MHz to Events 33MHz - Fast GATEA20 - Serial IRQ Interface Compatible with Serial- - Fast CPU RESET ized IRQ Support for PCI Systems - Multiple Clock Sources and Operating Fre- - 15 Direct IRQs quencies - ACPI SCI Interface - IDLE and SLEEP Modes - nSMI output and supporting PM registers - Trace FIFO Debug Port - Shadowed write only registers Accurate Fail-Safe Ring Oscillator Internal 64K SRAM in MEC1310 - Single Clock source for most 8051 and SIO - Loaded at VCC1 power from the HOST/8051 functions SPI Memory Interface - Provides 2% frequency accuracy - Provides 64KB of 8051 program space - Lock Bit provides status - 32k-Byte region shared with 8051data space - 32.768KHz-input clock HOST/8051 SPI Memory Interface Single ended input - 3-pin Full Duplex serial communication inter- Compatible with south bridge SUSCLK/ face. RSMRST gating rules - One Chip Select Pins replacement 32K distribution available when RSMRST is asserted - Fully 8051 Controlled Very low power state with only external 32K clock - Hardware Support for two SPI Flash Configu- distributed rations: Integrated Standby Power Reset Generator Switched SPI Flash Configuration - VCC1 RST open drain output Parallel Shared SPI Flash Configuration - Accepts External driven Reset Debug Programming Interface VCC0 Backed Resources Two Power Planes - 64 Byte VCC0 Backed Registers - Low Standby Current in Sleep Mode - VCC0 Backed Status Register Three ACPI Embedded Controller Interface 2 Three 8584-Style I C/SMBus Controllers Configuration Register Set Compatible with ISA 2 Plug-and-Play Standard (Version 1.0a) - 8051 Controlled Logic Allows I C/SMBus Master or Slave Operation High-Performance Embedded 8051 Keyboard 2 and System Controller -I C/SMBus Controllers are Fully Operational on Standby Power - Provides System Power Management - Two Controllers with 2 Sets of Dedicated Pins - System Watch Dog Timer (WDT) 2 per I C/SMBus Controller - 8042 Style Host Interface - One Controller with one Set of Dedicated - Supports Interrupt and Polling Access 2 Pins per I C/SMBus Controller - 1024 Boot /ROM Four independent Hardware Driven PS/2 Ports - 256 Bytes Data RAM - GPIO signal function associated with each - On-Chip Memory-Mapped Control Registers pin - Access to VCC0 Backed Registers PECI Interface 2.0 - Up to 18x8 Keyboard Scan Matrix 2014 Microchip Technology Inc. DS00001768A-page 1MEC1310 56 General Purpose I/O Pins Description - Maskable Hardware Wake-Event Capable The MEC1310 is a 128-pin 3.3V LPC-based ACPI 2.0 - Programmable Open-Drain/Push-Pull Out- and PC99/PC2001 compliant Notebook I/O Controller. puts See FIGURE 1: MEC1310 Block Diagram on page 4. 7 General-Purpose Outputs The MEC1310 incorporates a high-performance 8051- Four Programmable Pulse-Width Modulator Out- based keyboard and system controller with internal puts embedded 64K SRAM a 1K byte Boot ROM, and 64- - Independent Clock Rates bytes battery backed registers. The embedded 64K - 6-Bit Duty Cycle Granularity SRAM is loaded via HOST/8051 SPI Memory Inter- face. The HOST/8051 SPI Memory Interface can be - Operational in both Full on and Standby configured in Switched SPI Flash Configuration or Par- modes allel Shared SPI Flash Configuration. Dual Fan Tachometer Inputs The MEC1310 has four PS/2 ports an 16C550A-com- RPM-Based Fan Speed Control Algorithm patible 2 pin UART for Debug Port three 8584-style - Utilizes one TACH input and one PWM output 2 I C/SMBus controllers with two selectable ports per - 3% accurate from 500 RPM to 16k RPM controller a Serial IRQ peripheral agent interface - Automatic Tachometer feedback three ACPI Embedded Controller Interface General - Aging Fan or Invalid Drive Detection Purpose I/O pins and seven General Purpose Outputs - Spin Up Routine four independently programmable pulse width modula- tors dual fan control through the implementation of two - Ramp Rate Control fan tachometer input pins, RPM-PWM block with one RPM-based Fan Speed Control Algorithm tachometer input and one PWM output hardware mon- Debug Port (UART) itoring of a PWM input and maskable hardware wake- - High-Speed 16550A-Compatible UART with up events one BC-Link Combined High Speed/Low 16-Byte Send/Receive FIFOs Speed Bus Master Controller 5 channel Analog to Dig- - Programmable Baud Rate Generator ital Converter. - Relocatable to 480 Different Base I/O The MEC1310 has two separate power planes to pro- Addresses vide instant on and system power management func- - 15 IRQ Options tions. Additionally, the MEC1310 incorporates sophisticated power control circuitry (PCC). The PCC BC-Link Interconnection Bus supports multiple low power down modes. Wake-up - Combined High Speed/Low Speed Bus Mas- events and ACPI-related functions are supported ter Controller through the SCI Interface. General Purpose Analog to Digital Converter (GP- The MEC1310 supports the ISA Plug-and-Play Stan- ADC) dard (Version 1.0a) and provides all the functionality for - 10-bit conversion precision current Windows O/Ss. The I/O Address and Hard- - 10-bit conversion per channel is completed in ware IRQ of each logical device in the MEC1310 may 10.91us be reprogrammed through the internal configuration - 5 ADC channels registers. There are 480 I/O address location options 10-bit Conversion with 25.78 mV resolution and 15 IRQs for each logical device. 0 to 3.3 VDC Conversion Range - Channel 0 has a 5 volt tolerant input - Optional continuous sampling at a program- mable rate - Selectable VREF source on a per Channel Basis VREF pin or AVCC 128-Pin VTQFP RoHS Compliant Package DS00001768A-page 2 2014 Microchip Technology Inc.