MT90869
Flexible 16 K Digital Switch (F16kDX)
Data Sheet
December 2010
Features
Ordering Information
16,384-channel x 16,384-channel non-blocking
unidirectional switching.The Backplane and
MT90869AG 272 Ball PBGA Trays
Local inputs and outputs can be combined to
MT90869AG2 272 Ball PBGA* Trays
form a non-blocking switching matrix with 64
*Pb Free Tin/Silver/Copper
o
stream inputs and 64 stream outputs
-40 to +85 C
8,192-channel x 8,192-channel non-blocking
*Note: the package thickness is different than the
MT90869AG (see drawing at the end of the data
Backplane to Local stream switch
sheet).
8,192-channel x 8,192-channel non-blocking
Local to Backplane stream switch
Local port accepts 32 ST-BUS streams with
8,192-channel x 8,192-channel non-blocking
data rates of 2.048 Mb/s, 4.096 Mb/s,
Backplane input to Backplane output switch
8.192 Mb/s or 16.384 Mb/s, in any combination
8,192-channel x 8,192-channel non-blocking
Per-stream channel and bit delay for Local input
Local input to Local output stream switch
streams
Rate conversion on all data paths, Backplane to
Per-stream channel and bit delay for Backplane
Local, Local to Backplane, Backplane to
input streams
Backplane and Local to Local streams
Per-stream advancement for Local output
Backplane port accepts 32 ST-BUS streams
streams
with data rates of 2.048 Mb/s, 4.096 Mb/s,
Per-stream advancement for Backplane output
8.192 Mb/s or 16.384 Mb/s in any combination,
streams
or a fixed allocation of 16 streams at
Constant throughput delay for frame integrity
32.768 Mb/s
V V V RESET ODE
DD_IO DD_CORE SS (GND)
Backplane Data Memories Local
BSTi0-31
LSTi0-31
Interface
(8,192 channels)
Backplane
Backplane Local Local
Interface
Connection Memory Connection Memory Interface
(8,192 locations) (8,192 locations) LSTo0-31
BSTo0-31
LCST0-3
BCST0-3
Local Data Memories
BORS
(8,192 channels)
LORS
FP8o
Backplane
FP8i
Local
Timing Unit
FP16o
Timing
C8o
Unit
C16o
PLL Microprocessor Interface
Test Port
C8i
and Internal Registers
V
DD_PLL
DS CS R/W A14-A0 DTA D15-D0 TMS TDi TDo TCK TRST
Figure 1 - MT90869 Functional Block Diagram
1
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Copyright 2002-2010, Zarlink Semiconductor Inc. All Rights Reserved.MT90869 Data Sheet
Per-channel high impedance output control for Local and Backplane streams
Per-channel driven-high output control for local and backplane streams
High impedance-control outputs for external drivers on backplane and local port
Per-channel message mode for local and backplane output streams
Connection memory block programming for fast device initialization
BER testing for local and backplane ports.
Automatic selection between ST-BUS and GCI-BUS operation
Non-multiplexed Motorola microprocessor interface
Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
Memory Built-In-Self-Test (BIST), controlled via microprocessor registers
1.8 V core supply voltage
3.3 V I/O supply voltage
5 V tolerant inputs, outputs and I/Os
Per stream subrate switching at 4 bit, 2 bit and 1 bit depending on stream data rate
Applications
Central Office Switches (Class 5)
Mediation Switches
Class-independent switches
Access Concentrators
Scalable TDM-Based Architectures
Digital Loop Carriers
2
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