2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM
Features
DDR3 SDRAM ULP Mini-UDIMM
MT9JBF25672AKZ 2GB
Figure 1: 244-Pin ULP Mini-UDIMM
Features
Module height: 17.9mm (0.705in)
DDR3 functionality and operations supported as
defined in the component data sheet
244-pin, ultra-low profile, 17.9mm, mini-unbuffered
dual in-line memory module (ULP Mini-UDIMM)
Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
Options Marking
2GB (256 Meg x 72)
Operating temperature
V = 1.5V 0.075V
DD
Commercial (0C T +70C) None
A
V = 3.03.6V
DDSPD 1
Industrial (40C T +85C) I
A
Supports ECC error detection and correction
Package
Nominal and dynamic on-die termination (ODT) for
244-pin halogen-free ULP Mini- Z
data, strobe, and mask signals
UDIMM
Frequency/CAS latency
Single-rank
2
1.25ns @ CL = 11 (DDR3-1600) -1G6
On-board I C temperature sensor with integrated
1.5ns @ CL = 9 (DDR3-1333) -1G4
serial presence-detect (SPD) EEPROM
1.87ns @ CL = 7 (DDR3-1066) -1G1
8 internal device banks
Note: 1. Contact Micron for industrial temperature
Fixed burst chop (BC) of 4 and burst length (BL) of 8
module offerings.
via the mode register set (MRS)
Selectable BC4 or BL8 on-the-fly (OTF)
Gold edge contacts
Halogen-free
Fly-by topology
Terminated control, command, and address bus
Table 1: Key Timing Parameters
Data Rate (MT/s) t t t
Speed Industry RCD RP RC
Grade Nomenclature CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 (ns) (ns) (ns)
-1G6 PC3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125
-1G4 PC3-10600 1333 1333 1066 1066 800 667 13.125 13.125 49.125
-1G1 PC3-8500 1066 1066 800 667 13.125 13.125 50.625
-1G0 PC3-8500 1066 800 667 15 15 52.5
-80B PC3-6400 800 667 15 15 52.5
PDF: 09005aef83e0c154 Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
jbf9c256x72akz.pdf - Rev. F 5/13 EN 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM
Features
Table 2: Addressing
Parameter 2GB
Refresh count 8K
Row address 32K A[14:0]
Device bank address 8 BA[2:0]
Device configuration 2Gb (256 Meg x 8)
Column address 1K A[9:0]
Module rank address 1 S0#
Table 3: Part Numbers and Timing Parameters 2GB Modules
1
Base device: MT41J256M8, 2Gb DDR3 SDRAM
Module Module Memory Clock/ Clock Cycles
2 t t
Part Number Density Configuration Bandwidth Data Rate (CL- RCD- RP)
MT9JBF25672AK(I)Z-1G6__ 2GB 256 Meg x 72 12.8 GB/s 1.25ns/1600 MT/s 11-11-11
MT9JBF25672AK(I)Z-1G4__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9
MT9JBF25672AK(I)Z-1G1__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7
Notes: 1. The data sheet for the base device can be found on Microns Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT9JBF25672AKZ-1G4K1.
PDF: 09005aef83e0c154 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
jbf9c256x72akz.pdf - Rev. F 5/13 EN 2010 Micron Technology, Inc. All rights reserved.